ci130x_scu.h

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#ifndef CI130X_SCU_H
#define CI130X_SCU_H

#include "ci130x_system.h"
#include "sdk_default_config.h"
#include <stdbool.h>

#ifdef __cplusplus
extern "C" {
#endif 

// 注意，为了使CODE在多种采样率下都能得到整数倍分频，驱动中会自动对主频做一些调整（+/-4092MHz以内），所以实际运行频率肯能与这里配置的频率有差异。
// 准确频率可以通过调用 "dpmu_get_pll_frequency()" 函数获取。

#if USE_EXTERNAL_CRYSTAL_OSC
#define MAIN_FREQUENCY          240000000     
#else
#define MAIN_FREQUENCY          200000000     
#endif

#define SRC_FREQUENCY_NORMAL    12288000U     
#define SRC_FREQUENCY_LOWPOWER  12288000U

typedef enum
{
    QSPI_MODE_BOOT = 1,
    QSPI_MODE_NOMAL = 0,
}Qspi_Mode_t;

typedef enum
{
    NMI_IRQ_IWGD    = 0x1,
    NMI_IRQ_WWGD    = 0x2,
    NMI_IRQ_EXT0    = 0x3,
    NMI_IRQ_EXT1    = 0x4,
    NMI_IRQ_TIMER0  = 0x5,
    NMI_IRQ_TIMER1  = 0x6,
    NMI_IRQ_UART0   = 0x7,
    NMI_IRQ_UART1   = 0x8,
    NMI_IRQ_UART2   = 0x9,
    NMI_IRQ_PA      = 0xA,
    NMI_IRQ_PB      = 0xB,
    NMI_IRQ_PC      = 0xC,
    NMI_IRQ_VDT     = 0xC,
    NMI_IRQ_V11_OK  = 0xE,
    NMI_IRQ_ADC     = 0xF,
}Nmi_Irq_t;

typedef enum
{
    SLEEPING_GATE    = 0,
    SLEEPDEEP_GATE   = 1,
    CPU_CORECLK_GATE = 2,
    STCLK_GATE       = 3,
    SRAM0_GATE       = 4,
    SRAM1_GATE       = 5,
    SRAM2_GATE       = 6,
    SRAM3_GATE       = 7,
    SRAM4_GATE       = 8,
    SRAM5_GATE       = 9,
    SRAM6_GATE       = 10,
    ROM_GATE         = 11,
}Sys_Clk_Gate_t;

typedef enum
{
    FIRST_FUNCTION = 0,  
    SECOND_FUNCTION = 1, 
    THIRD_FUNCTION = 2,  
    FORTH_FUNCTION = 3,  
    FIFTH_FUNCTION = 4,  
    SIXTH_FUNCTION = 5,  
}IOResue_FUNCTION;

typedef enum
{
    DIGITAL_MODE = 0,   
    ANALOG_MODE = 1,    
}ADIOResue_MODE;

typedef enum
{
/***-----PAD-----****************----analgo--****----1st-----****---2nd-----****----3rd----****----4th----****----5th----****----6th----****/
    PA0                  = 0,   
    PA1                  = 1,   
    BOOT_SEL_0_PAD       = 2,   
    SPI0_CS_PAD          = 3,   
    SPI0_D1_PAD          = 4,   
    SPI0_D2_PAD          = 5,   
    PA2                  = 6,   
    PA3                  = 7,   
    PA4                  = 8,   
    PA5                  = 9,   
    PA6                  = 10,  
    PA7                  = 11,  
    PB0                  = 12,  
    PB1                  = 13,  
    PB2                  = 14,  
    PB3                  = 15,  
    PB4                  = 16,  
    PB5                  = 17,  
    PB6                  = 18,  
    PB7                  = 19,  
    PC0                  = 20,  
    KEY_RSTN_PAD         = 21,  
    TEST_EN_PAD          = 22,  
    SPI0_D0_PAD          = 23,  
    SPI0_CLK_PAD         = 24,  
    SPI0_D3_PAD          = 25,  
    PC1                  = 26,  
    PC2                  = 27,  
    PC3                  = 28,  
    PC4                  = 29,  
    PC5                  = 30,  
    PD0                  = 31,  
    PD1                  = 32,  
    PD2                  = 33,  
    PD3                  = 34,  
    PD4                  = 35,  
    PD5                  = 36,  
}PinPad_Name;

typedef enum
{
    IISNum0    = 0,
    IISNum1_RX = 1,
    IISNum1_TX = 2,
    IISNum2    = 3
}IISNumx;

typedef enum
{
    IIS_SLAVE = 1,   
    IIS_MASTER = 0,
}IIS_Mode_Sel_t;

typedef enum
{
    IIS_MCLK_MODENULL = 0,
    IIS_MCLK_IN = 1,        
    IIS_MCLK_OUT = 2,       
}IIS_Mclk_Mode_t;

typedef enum
{
    IIS_SCKLRCK_MODENULL = 0,
    IIS_SCKLRCK_IN = 1,     
    IIS_SCKLRCK_OUT = 2,    
}IIS_SckLrck_Mode_t;

typedef enum
{
    DMAINT_SEL_CHANNEL0   = 0,
    DMAINT_SEL_CHANNEL1   = 1,
    DMAINT_SEL_CHANNELALL = 2,
}DmaInt_Sel_t;

typedef enum
{
    DTR_CLK_SEL_SRC_CLK = 0,
    DTR_CLK_SEL_PLL_CLK  = 1,
}Dtr_Clk_Sel_t;

typedef enum
{
    IIS_SRC_SOURCE_IPCORE   = 0,
    IIS_SRC_SOURCE_EXT_OSC  = 1,
    IIS_SRC_SOURCE_INTER_RC = 2,
    IIS_SRC_SOURCE_PAD_IN   = 3,
}IIS_Src_Source_t;

typedef enum
{
    IIS_MCLK_FS_128   = 0,
    IIS_MCLK_FS_192   = 1,
    IIS_MCLK_FS_256   = 2,
    IIS_MCLK_FS_384   = 3,
}IIS_Mclk_Fs_t;

typedef enum
{
    IIS_SCK_LRCK_WID_32  = 0,
    IIS_SCK_LRCK_WID_64  = 1,
}IIS_Sck_Lrck_Wid_t;

typedef enum
{
    IIS_MCLK_SOURCE_SRC0    = 0,
    IIS_MCLK_SOURCE_SRC1    = 1,
    IIS_MCLK_SOURCE_SRC2    = 2,
    IIS_MCLK_SOURCE_PAD_IN  = 3,
}IIS_Mclk_Source_t;

typedef enum
{
    IIS_MCLK_MCLK0    = 0,
    IIS_MCLK_MCLK1    = 1,
    IIS_MCLK_MCLK2    = 2,
}IIS_Mclk_t;

typedef enum
{
    IIS_CLK_SOURCE_MCLK0     = 0,
    IIS_CLK_SOURCE_MCLK1     = 1,
    IIS_CLK_SOURCE_MCLK2     = 2,
    IIS_CLK_SOURCE_PAD_IN    = 3,
    IIS_CLK_SOURCE_CODEC_AD  = 4,
    IIS_CLK_SOURCE_CODEC_DA  = 5,
    IIS_CLK_SOURCE_PDM       = 6,
}IIS_Clk_Source_t;

typedef enum
{
    CODEC_DAC_DATA_FROM_IIS1_TX   = 0,
    CODEC_DAC_DATA_FROM_PAD_IN    = 1,
    CODEC_DAC_DATA_FROM_CODEC_ADC = 2,
    CODEC_DAC_DATA_FROM_PDM       = 3
}Codec_Dac_Data_Sel_t;

typedef enum
{
    PAD_IIS_DATA_FROM_IIS0_TX   = 0,
    PAD_IIS_DATA_FROM_IIS1_TX   = 1,
    PAD_IIS_DATA_FROM_CODEC_ADC = 2,
    PAD_IIS_DATA_FROM_PDM       = 3
}Pad_IIS_Data_Sel_t;

typedef enum
{
    IIS_CLK_MODE_OUTPUT    = 0,
    IIS_CLK_MODE_INPUT     = 1,
}IIS_Clk_Mode_t;

typedef enum
{
    CODEC_CHANNEL_AD    = 0,
    CODEC_CHANNEL_DA    = 1,
}Codec_Channel_t;

typedef struct
{
    IIS_Src_Source_t source;     
    uint32_t source_div;         
}IIS_Src_Config_t;

typedef struct
{
    IIS_Mclk_t mclk;             
    IIS_Mclk_Source_t src;       
    IIS_Mclk_Fs_t fs;            
    IIS_Sck_Lrck_Wid_t sck_lrck; 
}IIS_Mclk_Config_t;

typedef struct
{
    IISNumx device_select;       
    IIS_Mode_Sel_t model_sel;    
    IIS_Src_Config_t src_cfg;    
    IIS_Mclk_Config_t mclk_cfg;  
    IIS_Clk_Source_t clk_cfg;    
    IIS_Mclk_Mode_t mclk_mode;   
    IIS_SckLrck_Mode_t clk_mode; 
}IIS_Clk_ConfigTypedef;

void scu_unlock_system_config(void);

void scu_unlock_reset_config(void);

void scu_unlock_clk_config(void);

void scu_lock_system_config(void);

void scu_lock_clk_config(void);

void scu_lock_reset_config(void);

int32_t scu_set_device_gate(uint32_t device_base, int32_t gate);

int32_t scu_set_device_reset(uint32_t device_base);

int32_t scu_set_device_reset_release(uint32_t device_base);

int32_t scu_get_system_reset_state(void);

int32_t scu_set_ext_wakeup_int(Ext_Num num, FunctionalState cmd);

int32_t scu_clear_ext_int_state(Ext_Num num);

void scu_set_ext_filter_config(Ext_Num num,FunctionalState cmd,uint32_t param);

int8_t scu_para_en_disable(uint32_t device_base);

int8_t scu_para_en_enable(uint32_t device_base);

int32_t scu_set_div_parameter(uint32_t device_base,uint32_t div_num);

void scu_spiflash_no_boot_set(void);

void scu_run_in_flash(void);

void scu_run_not_in_flash(void);

void scu_set_dma_mode(DmaInt_Sel_t channel);

void scu_sel_dtrflash_clk(Dtr_Clk_Sel_t clk);

void scu_wait_pll_lock_state();

void scu_iis_src_config(IIS_Src_Config_t *config,IIS_Mclk_Source_t src);

void scu_iis_mclk_Config(IIS_Mclk_Config_t *config);

void scu_iis_pad_mclk_config(IIS_Mclk_Source_t src, IIS_Clk_Mode_t mode);

void scu_iis_codec_mclk_config(Codec_Channel_t channel, IIS_Mclk_Source_t src);

void scu_iis_pdm_mclk_config(IIS_Mclk_Source_t src);

void scu_iis_clk_config(IISNumx device, IIS_Clk_Source_t clk_source);

void scu_iis_pad_clk_config(IIS_Clk_Source_t clk_source, IIS_Clk_Mode_t mode);

void scu_iis_codec_dac_data_config(Codec_Dac_Data_Sel_t src);

void scu_iis_pad_data_config(Pad_IIS_Data_Sel_t src);

void iis_clk_config(IIS_Clk_ConfigTypedef* config);

void scu_rc_trim_en(bool en);

void scu_rc_trim_state_clear(void);

uint8_t scu_get_rc_trim_state(void);

uint8_t scu_get_rc_trim_c_value(void);

uint8_t scu_get_rc_trim_f_value(void);

void scu_set_wwdg_halt();

void scu_clean_wwdg_halt();

int32_t scu_set_system_clk_gate(Sys_Clk_Gate_t base,FunctionalState gate);

void scu_nmi_irq_cfg(Nmi_Irq_t irq);

void dsu_init(unsigned int addr);

#ifdef __cplusplus
}
#endif 

#endif /*CI130X_SCU_H*/

/***************** (C) COPYRIGHT Chipintelli Technology Co., Ltd. *****END OF FILE****/