ci130x_spiflash.h

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#ifndef _CI130X_SPIFLASH_H_
#define _CI130X_SPIFLASH_H_

#include "ci130x_system.h"

#ifdef __cplusplus
extern "C" {
#endif

#ifndef SPI0FIFO_BASE
#define SPI0FIFO_BASE 0x60000000
#endif

#define FLASH_MSF (0)
typedef enum
{
    QSPI0 = HAL_DTRFLASH_BASE,
}spic_base_t;

typedef enum
{
    SPIC_CMD_CODE_WRITE_ENABLE                  = 0x06,      
    SPIC_CMD_CODE_READMANUFACTURERIDDEVICEID    = 0x90,     
    SPIC_CMD_CODE_READJEDECID                   = 0x9F,     
    SPIC_CMD_CODE_READSTATUSREG1                = 0x05,     
    SPIC_CMD_CODE_READSTATUSREG2                = 0x35,     
    SPIC_CMD_CODE_READSTATUSREG3                = 0x15,     
    SPIC_CMD_CODE_SECTORERASE4K                 = 0x20,     
    SPIC_CMD_CODE_BLOCKERASE32K                 = 0x52,     
    SPIC_CMD_CODE_BLOCKERASE64K                 = 0xd8,     
    SPIC_CMD_CODE_CHIPERASE                     = 0xc7,     
    SPIC_CMD_CODE_PAGEPROGRAM                   = 0x02,     
    SPIC_CMD_CODE_QUADINPUTPAGEPROGRAM          = 0x32,     
    SPIC_CMD_CODE_WRSTATUSREG                   = 0x01,     
    SPIC_CMD_CODE_WRSTATUSREG2                  = 0x31,     
    SPIC_CMD_CODE_WRSTATUSREG3                  = 0x11,     
    SPIC_CMD_CODE_READDATA                      = 0x03,     
    SPIC_CMD_CODE_FASTREAD                      = 0x0b,     
    SPIC_CMD_CODE_FASTREADDUALOUTPUT            = 0x3b,     
    SPIC_CMD_CODE_FASTREADQUADOUTPUT            = 0x6b,     
    SPIC_CMD_CODE_FASTREADQUADIO                = 0xeb,     
    SPIC_CMD_CODE_POWERDOWN                     = 0xb9,     
    SPIC_CMD_CODE_RELEASEPOWERDOWN              = 0xab,     
    SPIC_CMD_CODE_ENABLERESET                   = 0x66,     
    SPIC_CMD_CODE_RESET                         = 0x99,     
    SPIC_CMD_CODE_READ_UNIQUE_ID                = 0x4b,     
    SPIC_CMD_CODE_ERASE_SECURITY_REG            = 0x44,     
    SPIC_CMD_CODE_WRITE_SECURITY_REG            = 0x42,     
    SPIC_CMD_CODE_READ_SECURITY_REG             = 0x48,     
    SPIC_CMD_CODE_WRITE_EXTENDED_ADDR_REG       = 0xC5,     
    SPIC_CMD_CODE_READ_EXTENDED_ADDR_REG        = 0xC8,     
    SPIC_CMD_CODE_ENABLE_QUAD                   = 0x38,     
    SPIC_CMD_CODE_DISABLE_QUAD                  = 0xFF,     
}spic_cmd_code_t;

typedef enum
{
    SPIC_SECURITY_REG1 = 0,
    SPIC_SECURITY_REG2 = 1,
    SPIC_SECURITY_REG3 = 2,
}spic_security_reg_t;

int32_t flash_init(spic_base_t spic);
int32_t spic_read_unique_id(spic_base_t spic,uint8_t* unique);
int32_t spic_read_jedec_id(spic_base_t spic,uint8_t* jedec);
int32_t spic_erase_security_reg(spic_base_t spic,spic_security_reg_t reg);
int32_t spic_write_security_reg(spic_base_t spic,spic_security_reg_t reg,
                              uint32_t buf,uint32_t addr,uint32_t size);
int32_t spic_read_security_reg(spic_base_t spic,spic_security_reg_t reg,
                              uint32_t buf,uint32_t addr,uint32_t size);
int32_t spic_security_reg_lock(spic_base_t spic,spic_security_reg_t reg);
int32_t flash_erase(spic_base_t spic,uint32_t addr,uint32_t size);
int32_t flash_write(spic_base_t spic,uint32_t addr,uint32_t buf,uint32_t size);
int32_t flash_read(spic_base_t spic,uint32_t buf,uint32_t addr,uint32_t size);
//int32_t dnn_mode_config(spic_base_t spic,uint32_t start_addr,uint32_t size);
//int32_t flash_dnn_mode(spic_base_t spic,FunctionalState cmd);
//uint32_t flash_check_mode(spic_base_t spic);
//int32_t spic_quad_mode(spic_base_t spic);
//int32_t spic_erase(spic_base_t spic,spic_cmd_code_t code,uint32_t addr);
int32_t spic_protect(spic_base_t spic,FunctionalState cmd);
//int32_t flash_is_dnn_mode(spic_base_t spic);
//int32_t spic_reset(spic_base_t spic);
int32_t spic_xipconfig(spic_base_t spic);
int32_t flash_clk_div_init(spic_base_t spic);

#ifdef __cplusplus
}
#endif

#endif