ci13lc_scu.h

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#ifndef CI13LC_SCU_H
#define CI13LC_SCU_H

#include <stdbool.h>
#include "ci_system.h"
#include "sdk_default_config.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef enum
{
    QSPI_MODE_BOOT = 1,
    QSPI_MODE_NOMAL = 0,
}Qspi_Mode_t;

typedef enum
{
    NMI_IRQ_IWDG    = 0x1,
    NMI_IRQ_EXT0    = 0x3,
    NMI_IRQ_EXT1    = 0x4,
    NMI_IRQ_TIMER0  = 0x5,
    NMI_IRQ_TIMER1  = 0x6,
    NMI_IRQ_UART0   = 0x7,
    NMI_IRQ_UART1   = 0x8,
    NMI_IRQ_UART2   = 0x9,
    NMI_IRQ_PA      = 0xA,
    NMI_IRQ_PB      = 0xB,
    NMI_IRQ_PC      = 0xC,
    NMI_IRQ_VDT     = 0xD,
    NMI_IRQ_V11_OK  = 0xE,
}Nmi_Irq_t;

typedef enum
{
    SLEEPING_GATE    = 0,
    SLEEPDEEP_GATE   = 1,
    CPU_CORECLK_GATE = 2,
    STCLK_GATE       = 3,
    SRAM0_GATE       = 4,
    SRAM1_GATE       = 5,
    SRAM2_GATE       = 6,
    SRAM3_GATE       = 7,
    SRAM4_GATE       = 8,
    SRAM5_GATE       = 9,
    ROM_GATE         = 11,
}Sys_Clk_Gate_t;

typedef enum
{
    WAKRUP_MASK_EXT0    = 1,
    WAKRUP_MASK_EXT1    = 2,
    WAKRUP_MASK_IWDG    = 3,
    WAKRUP_MASK_TIMER0  = 5,
    WAKRUP_MASK_TIMER1  = 6,
    WAKRUP_MASK_UART0   = 7,
    WAKRUP_MASK_UART1   = 8,
    WAKRUP_MASK_UART2   = 9,
    WAKRUP_MASK_GPIO0   = 10,
    WAKRUP_MASK_GPIO1   = 11,
    WAKRUP_MASK_GPIO2   = 12,
    WAKRUP_MASK_IIS0    = 13,
    WAKRUP_MASK_VDT     = 14,
    WAKRUP_MASK_V11_OK  = 15,
    WAKRUP_MASK_IISDMA  = 18,
}Wakeup_Mask_t;

typedef enum
{
    FIRST_FUNCTION = 0,  
    SECOND_FUNCTION = 1, 
    THIRD_FUNCTION = 2,  
    FORTH_FUNCTION = 3,  
    FIFTH_FUNCTION = 4,  
    SIXTH_FUNCTION = 5,  
    SEVENTH_FUNCTION = 6,
}IOResue_FUNCTION;

typedef enum
{
    DIGITAL_MODE = 0,   
    ANALOG_MODE = 1,    
}ADIOResue_MODE;

typedef enum
{
    IISNum0    = 0,
    IISNum1_RX = 1,
    IISNum1_TX = 2,
}IISNumx;

typedef enum
{
    IIS_SLAVE = 1,
    IIS_MASTER = 0,
}IIS_Mode_Sel_t;

typedef enum
{
    IIS_MCLK_MODENULL = 0,
    IIS_MCLK_IN = 1,        
    IIS_MCLK_OUT = 2,       
}IIS_Mclk_Mode_t;

typedef enum
{
    IIS_SCKLRCK_MODENULL = 0,
    IIS_SCKLRCK_IN = 1,     
    IIS_SCKLRCK_OUT = 2,    
}IIS_SckLrck_Mode_t;

typedef enum
{
    DTR_CLK_SEL_SRC_CLK = 0,
    DTR_CLK_SEL_PLL_CLK  = 1,
}Dtr_Clk_Sel_t;

typedef enum
{
    IIS_SRC_SOURCE_IPCORE   = 0,
    IIS_SRC_SOURCE_EXT_OSC  = 1,
    IIS_SRC_SOURCE_INTER_RC = 2,
    IIS_SRC_SOURCE_PAD_IN   = 3,
}IIS_Src_Source_t;

typedef enum
{
    IIS_MCLK_FS_128   = 0,
    IIS_MCLK_FS_192   = 1,
    IIS_MCLK_FS_256   = 2,
    IIS_MCLK_FS_384   = 3,
}IIS_Mclk_Fs_t;

typedef enum
{
    IIS_SCK_LRCK_WID_32  = 0,
    IIS_SCK_LRCK_WID_64  = 1,
}IIS_Sck_Lrck_Wid_t;

typedef enum
{
    IIS_MCLK_SOURCE_SRC0    = 0,
    IIS_MCLK_SOURCE_SRC1    = 1,
    IIS_MCLK_SOURCE_PAD_IN  = 3,
    IIS_MCLK_SOURCE_NONE    = 4,
}IIS_Mclk_Source_t;

typedef enum
{
    IIS_MCLK_MCLK0    = 0,
    IIS_MCLK_MCLK1    = 1,
}IIS_Mclk_t;

typedef enum
{
    IIS_CLK_SOURCE_MCLK0     = 0,
    IIS_CLK_SOURCE_MCLK1     = 1,
    IIS_CLK_SOURCE_PAD_IN    = 3,
    IIS_CLK_SOURCE_CODEC_AD  = 4,
    IIS_CLK_SOURCE_CODEC_DA  = 5,
    IIS_CLK_SOURCE_NONE      = 6,
}IIS_Clk_Source_t;

typedef enum
{
    CODEC_DAC_DATA_FROM_IIS1_TX   = 0,
    CODEC_DAC_DATA_FROM_PAD_IN    = 1,
    CODEC_DAC_DATA_FROM_CODEC_ADC = 2,
}Codec_Dac_Data_Sel_t;

typedef enum
{
    PAD_IIS_DATA_FROM_IIS0_TX   = 0,
    PAD_IIS_DATA_FROM_IIS1_TX   = 1,
    PAD_IIS_DATA_FROM_CODEC_ADC = 2,
}Pad_IIS_Data_Sel_t;

typedef enum
{
    IIS_CLK_MODE_OUTPUT    = 0,
    IIS_CLK_MODE_INPUT     = 1,
}IIS_Clk_Mode_t;

typedef enum
{
    CODEC_CHANNEL_AD    = 0,
    CODEC_CHANNEL_DA    = 1,
}Codec_Channel_t;

typedef struct
{
    IIS_Src_Source_t source;     
    uint32_t source_div;         
}IIS_Src_Config_t;

typedef struct
{
    IIS_Mclk_t mclk;             
    IIS_Mclk_Source_t src;       
    IIS_Mclk_Fs_t fs;            
    IIS_Sck_Lrck_Wid_t sck_lrck; 
}IIS_Mclk_Config_t;

typedef struct
{
    IISNumx device_select;       
    IIS_Mode_Sel_t model_sel;    
    IIS_Src_Config_t src_cfg;    
    IIS_Mclk_Config_t mclk_cfg;  
    IIS_Clk_Source_t clk_cfg;    
    IIS_Mclk_Mode_t mclk_mode;   
    IIS_SckLrck_Mode_t clk_mode; 
}IIS_Clk_ConfigTypedef;

void scu_unlock_system_config(void);

void scu_unlock_reset_config(void);

void scu_unlock_clk_config(void);

void scu_lock_system_config(void);

void scu_lock_clk_config(void);

void scu_lock_reset_config(void);

int32_t scu_set_device_gate(uint32_t device_base, int32_t gate);

int32_t scu_set_device_reset(uint32_t device_base);

int32_t scu_set_device_reset_release(uint32_t device_base);

int32_t scu_get_system_reset_state(void);

int32_t scu_set_ext_wakeup_int(Wakeup_Mask_t num, FunctionalState cmd);

int32_t scu_clear_ext_int_state(Wakeup_Mask_t num);

void scu_set_ext_filter_config(Ext_Num num,FunctionalState cmd,uint32_t param);

int8_t scu_para_en_disable(uint32_t device_base);

int8_t scu_para_en_enable(uint32_t device_base);

int32_t scu_set_div_parameter(uint32_t device_base,uint32_t div_num);

void scu_spiflash_no_boot_set(void);

void scu_run_in_flash(void);

void scu_run_not_in_flash(void);

void scu_sel_dtrflash_clk(Dtr_Clk_Sel_t clk);

void scu_wait_pll_lock_state();

void scu_iis_src_config(IIS_Src_Config_t *config,IIS_Mclk_Source_t src);

void scu_iis_mclk_config(IIS_Mclk_Config_t *config);
void scu_iis_pad_mclk_config(IIS_Mclk_Source_t src, IIS_Clk_Mode_t mode);

void scu_iis_codec_mclk_config(Codec_Channel_t channel, IIS_Mclk_Source_t src);

void scu_iis_clk_config(IISNumx device, IIS_Clk_Source_t clk_source);

void scu_iis_pad_clk_config(IIS_Clk_Source_t clk_source, IIS_Clk_Mode_t mode);

void scu_iis_codec_dac_data_config(Codec_Dac_Data_Sel_t src);

void scu_iis_pad_data_config(Pad_IIS_Data_Sel_t src);

void iis_clk_config(IIS_Clk_ConfigTypedef* config);

int32_t scu_set_system_clk_gate(Sys_Clk_Gate_t base,FunctionalState gate);

void scu_nmi_irq_cfg(Nmi_Irq_t irq);

void scu_set_ext0_ext1_int(Ext_Num num,FunctionalState en);

void dsu_init(void);

#ifdef __cplusplus
}
#endif 

#endif /*CI13LC_SCU_H*/

/***************** (C) COPYRIGHT Chipintelli Technology Co., Ltd. *****END OF FILE****/