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引脚描述

CI1306芯片引脚图如图P-1所示:

CI1306芯片引脚图

图P-1 CI1306芯片引脚图

芯片各个引脚功能如下表描述:

表P-1 芯片引脚功能描述

Pin Number Pin name Pin type IO 5V-Tolerant IO power-on default state Description and alternate functions
1 VDD11 P - - 1.1V output or 1.1V Power supply, output apacitance/input capacitance is 4.7uF
2 XIN I - - 1. XIN (external crystal and oscillator interface, initial state at startup, no external crystal oscillator is required for normal application)
2. GPIO PA0
3. PWM5
3 XOUT O - - 1. XOUT(external crystal and oscillator interface, initial state at startup, no external crystal oscillator is required for normal application)
2. GPIO PA1
4 PD0 IO IN,T+D GPIO PD0
5 PD1 IO IN,T+D GPIO PD1
6 PA2 IO IN,T+D 1. GPIO PA2(Initial state at startup)
2. IIS_SDI
3. IIC_SDA
4. UART1_TX
5. PWM0
7 PA3 IO IN,T+D 1. GPIO PA3(Initial state at startup)
2. IIS_LRCLK
3. IIC_SCL
4. UART1_RX1
5. PWM1
8 PA4 IO IN,T+U 1. GPIO PA4(Initial state at startup)/PG_EN(Note1)
2. IIS_SDO
3. PWM2
9 PA5 IO IN,T+D 1. GPIO PA5(Initial state at startup)
2. IIS_SCLK
3. PDM_DAT
4. UART2_TX
5. PWM3
10 PA6 IO IN,T+D 1. GPIO PA6(Initial state at startup)
2. IIS_MCLK
3. PDM_CLK
4. UART2_RX
5. PWM4
11 PA7 IO IN,T+D 1. GPIO PA7(Initial state at startup)
2. PWM0
3. UART1_TX
4. EXT_INT[0]
12 PB0 IO IN,T+D 1. GPIO PB0(Initial state at startup)
2. PWM1
3. UART1_RX
4. EXT_INT[1]
13 PB1 IO IN,T+D 1. GPIO PB1(Initial state at startup)
2. PWM2
3. UART2_TX
14 PB2 IO IN,T+D 1. GPIO PB2(Initial state at startup)
2. PWM3
3. UART2_RX
15 PB3 IO IN,T+D 1. GPIO PB3(Initial state at startup)
2. PWM4
3. IIC_SDA
16 PB4 IO IN,T+D 1. GPIO PB4(Initial state at startup)
2. PWM5
3. IIC_SCL
17 PB5 IO IN,T+U 1. GPIO PB5(Initial state at startup)
2. UART0_TX
3. IIC_SDA
4. PWM1
18 PB6 IO IN,T+U 1. GPIO PB6(Initial state at startup)
2. UART0_RX
3. IIC_SCL
4. PWM2
19 PB7 IO IN,T+U 1. GPIO PB7(Initial state at startup)
2. UART1_TX
3. IIC_SDA
4. PWM3
20 PC0 IO IN,T+U 1. GPIO PC0(Initial state at startup)
2. UART1_RX
3. IIC_SCL
4. PWM4
21 PD3 IO - IN,T+D GPIO PD3
22 PD4 IO - IN,T+D GPIO PD4
23 TEST_EN I - - TEST Pin (Note2)
24 RSTn I - - Reset Pin ( Note3)
25 AIN5 IO IN,T+D 1. GPIO PC1(Initial state at startup)
2. UART2_TX
3. PWM3
4. PDM_DAT
5. ADC input channel 5
26 AIN4 IO IN,T+U 1. GPIO PC2(Initial state at startup)
2. UART2_RX
3. PWM2
4. PDM_CLK
5. ADC input channel 4
27 AIN3 IO IN,T+D 1. GPIO PC3(Initial state at startup)
2. IIC_SDA
3. PWM1
4. PDM_DAT
5. ADC input channel 3
28 AIN2 IO IN,T+U 1. GPIO PC4(Initial state at startup)
2. IIC_SCL
3. PWM0
4. PDM_CLK
5. ADC input channel 2
29 PC5 IO IN,T+D GPIO PC5/BOOT_SEL (Note4)
30 MICPL I - - Left Microphone P input
31 MICNL I - - Left Microphone N input
32 MICBIAS O - - Microphone bias output
33 MICPR I - - Right Microphone P input
34 MICNR I - - Right Microphone N input
35 VCM O - - VCM Output
36 AGND P - - Analog ground
37 HPOUT O - - DAC output
38 AVDD P - - 3.3V output or 3.3V analog power supply, output capacitance/input capacitance is 4.7uF
39 VIN5V P - - VIN5V is the PMU power supply input pin. The normal working input voltage range is 3.6V-5.5V. A 4.7uf input capacitor is connected externally. The maximum input voltage of this pin is 6.5V. Note that overvoltage and surge protection devices need to be added, such as a TVS and a 4.7 ohm resistor to protect against surge impact
40 VDD33 P - - 3.3V output, output capacitance/input capacitance is 4.7uF
41 GND P - - Ground PAD (Note5)

上表中 IO引脚的状态定义如下:

I 输入

O 输出

IO 双向

P 电源或地

T+D 三态正下拉

T+U 三态正上拉

OUT 上电默认为输出模式

IN 上电默认为输入模式

所有IO支持驱动能力可配,上下拉电阻可配。

Note1:PG_EN引脚根据上电时电平状态判断是否进行编程,高电平时启动编程功能。

Note2:TEST_EN是使能测试功能引脚,内部有下拉,当上电时检测该引脚输入电平,为低电平时芯片正常启动,为高电平时进入测试模式。

Note3:RSTn是外部复位输入引脚,拉低时间大于100uS时使能芯片复位。

Note4:BOOT_SEL引脚根据上电时电平状态判断系统启动的入口设备,低电平时从Flash启动,高电平时从SRAM启动。

Note5:QFN40封装底部有散热焊盘,使用时需要接到地。