Independent Watchdog (IWTD)¶
Function Introduction¶
The watchdog timer is a hardware timing circuit primarily used to monitor the system for faults caused by software anomalies. The independent watchdog module is based on a 32-bit down-counter, using a clock independent of PCLK. When the counter decrements to zero, an interrupt request is generated, and the counter reloads its initial value to begin counting down again. If the interrupt is not cleared before the counter reaches zero again, a reset request is generated, and the counter stops counting. Both interrupt and reset requests can be enabled or disabled via register configuration. When the interrupt request is disabled, the counter stops counting. Upon re-enabling the interrupt request, the counter reloads its initial value and resumes counting down.
To configure the software, 0x1ACCE551 must be written to the lock register to access other related registers.
Register Mapping¶
The base address for IWTD register mapping is 0x40032000. Detailed register mapping is shown in Table I-1.
| Offset | Name | Bit Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| 0x00 | WdogLoad | 32 | R/W | 0xFFFFFF | Initial count value register |
| 0x04 | WdogValue | 32 | RO | 0xFFFFFFFF | Count value register |
| 0x08 | WdogControl | 32 | R/W | 0x00000000 | Control register |
| 0x0C | WdogIntClr | 32 | WO | - | Interrupt clear register |
| 0x10 | WdogRIS | 32 | RO | 0x00000000 | Raw interrupt status register |
| 0x14 | WdogMIS | 32 | RO | 0x00000000 | Masking interrupt status register |
| 0xC00 | WdogLock | 32 | R/W | 0x00000000 | Lock register |
Count Initial Value Register (WdogLoad)¶
Offset: 0x00
Reset value: 0xFFFFFFFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | WdogLoad | 0xFFFFFFFF | R/W | Initial count register |
Count Value Register (WdogValue)¶
Offset: 0x04
Reset value: 0xFFFFFFFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | WdogValue | 0xFFFFFFFF | R/W | Count value register |
Control Register (WdogControl)¶
Offset: 0x08
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:2 | Reserved | 0x00000000 | R/W | Reserved |
| 1 | RESEN | 0 | R/W | Reset request enable: 0: Disable 1: Enable |
| 0 | INTEN | 0 | R/W | Interrupt request enable: 0: disable 1: enable |
Interrupt Clear Register (WdogIntClr)¶
Offset: 0x0C
Reset value:-
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | WdogIntClr | - | WO | Interrupt clear register: Write any value to this register to clear the interrupt request. The counter overloads the initial value to count down. |
Raw Interrupt Status Register (WdogRIS)¶
Offset: 0x10
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:1 | Reserved | 0x00000000 | RO | Reserved |
| 0 | WdogRIS | 0 | RO | Original interrupt status |
Masking Interrupt Status Register (WdogMIS)¶
Offset: 0x14
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:1 | Reserved | 0x00000000 | RO | Reserved |
| 0 | WdogMIS | 0 | RO | Masking interrupt status |
Lock Register (WdogLock)¶
Offset: 0xC00
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:2 | WdogLock | 0x00000000 | R/W | Lock register: Write 0x1ACCE551 to this register to write all other registers related to the module, otherwise you cannot write all other registers When reading this register: 0x00000000: all other registers can be written 0x00000001: all other registers cannot be written |