TIMER¶

Introduction¶

TIMER function is to repeatedly trigger timer events of the specified window within the specified time interval.

API¶

Function name	Description
timer_ Init	Initialize TIMER device
timer_ Start	Start TIMER device
timer_ Stop	Stop TIMER device
timer_ set_ Mode	Set TIMER device counting mode
timer_ event_ Start	TIMER device trigger event count
timer_ set_ count	TIMER sets the timing cycle
timer_ get_ Count	TIMER device obtains the count value
timer_ cascade_ Set	TIMER device setting cascading mode

TIMER name	Interrupt name	Interrupt service function	Description
TIMER0	TIMER0_ IRQn	TIMER0_ IRQHandler
TIMER1	TIMER1_ IRQn	TIMER1_ IRQHandler
TIMER2	TIMER2_ IRQn	TIMER2_ IRQHandler
TIMER3	TIMER3_ IRQn	TIMER3_ IRQHandler
AON_ TIMER0	AON_ TIM_ INT0_ IRQn	AON_ TIM_ INT0_ IRQHandler	HAL_ PWM4_ BASE can be regarded as AON_ TIMER0
AON_ TIMER1	AON_ TIM_ INT1_ IRQn	AON_ TIM_ INT0_ IRQHandler	HAL_ PWM5_ BASE can be regarded as AON_ TIMER1

Example¶

The following code configures and starts TIMER0, and the timer interrupts once in 1S:

void timer_ s(uint32_t s)
{
eclic_ irq_ enable(TIMER0_IRQn);
scu_ set_ device_ gate(HAL_TIMER0_BASE,ENABLE);
timer_ init_ t init;
init. mode = timer_ count_ mode_ auto;
init. div = timer_ clk_ div_ 0
init. width = timer_ iqr_ width_ f;
init. count = get_ apb_ clk() * s;
timer_ init(TIMER0,init);
timer_ start(TIMER0);
}

The following code configures and starts TIMER0, and the timer interrupts once every 1ms:

void timer_ ms(uint32_t ms)
{
eclic_ irq_ enable(TIMER0_IRQn);
scu_ set_ device_ gate(HAL_TIMER0_BASE,ENABLE);
timer_ init_ t init;
init. mode = timer_ count_ mode_ auto;
init. div = timer_ clk_ div_ 0
init. width = timer_ iqr_ width_ f;
init. count = (get_apb_clk() / 1000) * ms;
timer_ init(TIMER0,init);
timer_ start(TIMER0);
}

The following code configures and starts TIMER0, and 1us interrupts the timer once:

void timer_ us(uint32_t us)
{
eclic_ irq_ enable(TIMER0_IRQn);
scu_ set_ device_ gate(HAL_TIMER0_BASE,ENABLE);
timer_ init_ t init;
init. mode = timer_ count_ mode_ auto;
init. div = timer_ clk_ div_ 0
init. width = timer_ iqr_ width_ f;
init. count = (get_apb_clk() / 1000000) * us;
timer_ init(TIMER0,init);
timer_ start(TIMER0);
}

Warning

CI130X chip built-in 32-bit counter, counting range: 0x0 - 0xFFFFFFFF; If you need to set the timer for a longer time, you need to divide the frequency of the timer or use the cascade mode.

Frequently Asked Questions¶

TIMER timing range (TIMER module basic clock CLK_S=120000000Hz)

Frequency division coefficient: DIV (value range: 1, 2, 4, 16)

Count clock: CLK=CLK_ S/DIV Unit: Hz

Minimum timing: MIN=1s/CLK Unit: S

Maximum timing: MAX=0xFFFFFFFF * MIN Unit: S

For the above method, the maximum timing is about 9 minutes. If you need more time for timing, please use the timer cascade mode. The cascading mode is described as follows:

TODO:

Basic timer	Cascade timer
TIMER0	TIMER1\2\3
TIMER1	TIMER2\3
TIMER2	TIMER3
AON_ TIMER0	AON_ TIMER1

for instance: Now we take TIMER0 as the basic timer, set the clock frequency division coefficient to 16 (to maximize the timing here), set TIMER1, TIMER2, and TIMER3 in cascade mode, and set the count value of TIMER1, TIMER2, and TIMER3 as the maximum (0xFFFFFFFF). How long is the timing of each TIMER?

timer	Timing time
TIMER0	About 13 minutes
TIMER1	0xFFFFFFFF * About 13 minutes
TIMER2	0xFFFFFFFF * 0xFFFFFF * About 13 minutes
TIMER3	0xFFFFFFFF * 0xFFFFFF * 0xFFFFFFFF * About 13 minutes
AON_ TIMER0	About 13 minutes
AON_ TIMER1	0xFFFFFFFF * About 13 minutes