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Universal Timer And PWM Output

Function introduction

The universal timer can generate PWM wave output and timer interrupt signal. The two timer units can work independently as separate timers or be combined into a cascade timer. The timer unit counts down the 32-bit timer to generate periodic interrupts or PWM waveforms. When two timer units work in cascade, TIMER_ UNIT_ 0 as TIMER_ UNIT_ 1. Timer unit slave register TIMER_ SC decrement TIMER_ In SPWMC, the PWM output is set high, and when it decreases to 0, the PWM output is set low. At the same time, an interrupt signal with a configurable width is generated. Each timer unit has the following characteristics:

  • Multiple counting modes: single cycle, automatic restart and free counting mode
  • PWM output
  • Counting clock frequency division
  • Cascade mode
  • Can cause periodic interruption

The chip has four dedicated TIMERS (TIMER0 to TIMER3) and six dedicated PWM (PWM0 to PWM5).

Register Mapping

The base addresses of TIMER0/½/3 register mapping are 0x40018000, 0x40019000, 0x4001A000 and 0x4001B000 respectively, and the base addresses of PWM0/½ register mapping are 0x40014000, 0x40015000 and 0x40016000 respectively. See Table T-1 for specific register mapping.

Table T-1 TIMER and PWM Register Mapping

Offset Name Bit Width Type Reset Value Description
0x00 TIMER_ CFG 32 R/W 0x00000000 Configuration register
0x04 TIMER_ CFG1 32 R/W 0x00000010 Configuration register 1
0x08 TIMER_ EW 32 R/W 0x00000000 Event register
0x0C TIMER_ SC 32 R/W 0x00000000 Cycle register
0x10 TIMER_ CC 32 RO 0x00000000 Count value register
0x14 TIMER_ SPWMC 32 R/W 0x00000000 PWM cycle register (PWM only)
0x18 TIMER_ CFG0 32 R/W 0x00000000 Configuration register 0

Configuration register (TIMER_CFG)

Offset: 0x00

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:9 Reserved 0x00_ 0000 R/W Reserved
8: 7 TM 0x0 R/W Timer interrupt signal width:
0x0: by TIMER_ CFG1 [CT] Clear
0x1:2 clock cycles
0x2: 4 clock cycles
0x3: 8 clock cycles
6 TP 0 R/W Timer interrupt polarity:
0: high effective
1: low effective
5 CS 0 R/W Counting clock source:
0: PCLK
1: EXT_ CLK (special PWM connected to PCLK)
4: 2 CM 0x0 R/W Counting mode:
0x0: Single cycle mode
0x1: Automatic re counting mode
0x2: Free counting mode
0x3: Event counting mode
0x4-0x7: Reserved
1: 0 TS 0x0 R/W Counting clock frequency division:
0x0: no frequency division
0x1:2 frequency division
0x2:4 frequency division
0x3:16 frequency division

Configuration register 1 (TIMER_CFG1)

Offset: 0x04

Reset value: 0x00000010

Bit Field Name Reset Value Type Description
31:4 Reserved 0x0000001 R/W Reserved
3 RU 0 R/W TIMER_ Value saved in CC register:
0: count value before this position bit
1: current count value
2 CT 0 R Clear timer interrupt:
0: No effect
1: Clear timer interrupt
1 PC 0 R/W Pause Count:
0: Normal Count
1: Pause Count
0 RES 0 R Recount:
0: No effect
1: From TIMER_ SPWMC and TIMER_ SC overload, count down

Event Register (TIMER_EW)

Offset: 0x08

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:1 Reserved 0x00000000 R/W Reserved
0 EW 0 R/W Event counting overload. After a clock cycle, the bit is cleared automatically.
Event counting mode:
0: no effect
1: counter minus 1

Cycle register (TIMER_SC)

Offset: 0x0C

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:0 TIMER_ SC 0x00000000 R/W Timer cycle value

Count value register (TIMER_CC)

Offset: 0x10

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:0 TIMER_ CC 0x00000000 R/W Current count value

PWM cycle register (TIMER_SPWMC)

Offset: 0x14

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:0 TIMER_ SPWMC 0x00000000 R/W PWM cycle value

Configuration register 0 (TIMER_CFG0)

Offset: 0x18

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:3 Reserved 0x00000000 R/W Reserved
2 TRU_ EN 0 R/W Input signal TIMER_ RU enable:
0: TIMER_ RU invalid
1: TIMER_ TIMER when RU is 1_ CC update
1 Reversed 0 R/W Reserved
0 TSEL_ CLK 0 R/W Counting clock selection:
0: PCLK or EXT_ CLK
1: Cascaded clock