System Control Unit SCU¶
The system control unit is mainly responsible for the clock source of the chip, the generation and control of some clock signals, interrupt control and other functions. This module and the DPMU module together provide the basic functions of the chip such as clock control.
SCU Register Mapping¶
The base address of the system control unit register mapping is 0x40000000. See Table SCU-1 for details.
Table SCU-1 System Control Unit Register Mapping
| Offset | Name | Bit Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| 0x00 | SYS_CTRL_CFG | 32 | R/W | 0x00000401 | System control register |
| 0x0C | EXT_INT_CFG | 32 | R/W | 0x00000000 | External interrupt configuration register |
| 0x50 | SYSCFG_LOCK_CFG | 32 | R/W | 0x00000000 | System lock configuration register |
| 0x58 | CKCFG_LOCK_CFG | 32 | R/W | 0x00000000 | Clock configuration lock configuration register |
| 0x80 | CLKDIV_PARAM0_CFG | 32 | R/W | 0x1001808C | Frequency division parameter register 0 |
| 0x84 | CLKDIV_PARAM1_CFG | 32 | R/W | 0x00008208 | Frequency division parameter register 1 |
| 0xB0 | CLK_DIV_PARAM_EN_CFG | 32 | R/W | 0x00000000 | Frequency division parameter enable register |
| 0x11C | SYS_CLKGATE_CFG0 | 32 | R/W | 0x00000FFC | System clock gating configuration register |
| 0x124 | AHB_CLKGATE_CFG | 32 | R/W | 0x0000007F | AHB bus module clock gating configuration register |
| 0x128 | APB0_CLKGATE_CFG | 32 | R/W | 0x00007FFF | APB0 bus module clock gating configuration register |
| 0x12C | APB1_CLKGATE_CFG | 32 | R/W | 0x000001FF | APB1 bus module clock gating configuration register |
| 0x178 | SCU_STATE_REG | 32 | R/W | 0x00000001 | SCU status register |
| 0x190 | AHB_RESET_CFG | 32 | R/W | 0x0000007E | AHB bus module software reset configuration register |
| 0x194 | APB0_RESET_CFG | 32 | R/W | 0x00000FFF | APB0 bus module software reset configuration register |
| 0x198 | APB1_RESET_CFG | 32 | R/W | 0x000001FF | APB1 bus module software reset configuration register |
| 0x1DC | WAKEUP_MASK_CFG | 32 | R/W | 0x00000000 | Wake up Mask configuration register |
| 0x1F4 | INT_STATE_REG | 32 | R/W | 0x00000000 | Interrupt status register |
System Control Register (SYS_CTRL_CFG)¶
Offset: 0x00
Reset value: 0x00000401
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:11 | Reserved | 0x0 | RW | Reserved |
| 10 | DTR_CLK_SEL | 0x1 | RW | DTR controller clock source: 0: clock before PLL frequency multiplication 1: PLL clock |
| 9 | RUN_IN_FLASH_EN | 0x1 | RW | Control system program running in FLASH (enable Flash XIP function): 1: running in FLASH 0: not running in FLASH |
| 8:5 | Reserved | 0x1 | RW | Reserved |
| 4:1 | NMI_INT_CTRL | 0x0 | RW | Configure the CPU fast interrupt as the following interrupt source: 0: Reserved 1: INT_IWDG 2：INT_WWDG 3：INT_EXT0 4：INT_EXT1 5：INT_TIMER0 6：INT_TIMER1 7：INT_UART0 8：INT_UART1 9：INT_UART2 10：INT_GPIO0 11：INT_GPIO1 12：INT_GPIO2 13：INT_VDT 14：Reserved 15：INT_ADC |
| 0 | SPI_BOOT | 0x1 | RW | Enable the BOOT mode of the QSPI controller corresponding to Flash:, After the system is started, the SPI_If the BOOT bit is set to 0, the QSPI controller corresponding to Flash can restore to the normal mode, and the data in Flash can be read and written normally |
External Interrupt Configuration Register (EXT_INT_CFG)¶
Offset: 0x0C
Reset value: 0x00,000,000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:4 | Reserved | 0x0 | RW | Reserved |
| 3 | EXT1_INT_EN | 0x0 | RW | External Interrupt 1 Interrupt Enable: 1: A corresponding interrupt is generated when an external interrupt request occurs 0: The interrupt is not enabled |
| 2 | EXT0_INT_EN | 0x0 | RW | External Interrupt 0 Interrupt Enable: 1: A corresponding interrupt is generated when an external interrupt request occurs 0: Interrupt is not enabled |
| 1 | EXT1_INT_STATE | 0x0 | RW | External Interrupt 1 Status Bit: 1: External Interrupt Request Occurred 0: No External Interrupt Request Occurred Write 1 of this bit is cleared |
| 0 | EXT0_INT_STATE | 0x0 | RW | External Interrupt 0 Status Bit: 1: External Interrupt Request Occurred 0: No External Interrupt Request Occurred This bit is written to 1 and cleared |
System Lock Configuration Register (SYSCFG_LOCK_CFG)¶
Offset: 0x50
Reset value: 0x00,000,000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | SYSCFG_LOCK | 0x0 | RW | When the software configures the system, it is necessary to write 0x51AC0FFE to this register to unlock it before writing the configuration of each register of the system control unit. Reading the value of this register has the following meanings: 1: this register is unlocked and can be written 0: this register is not unlocked and cannot be written |
Clock Configuration Lock Configuration Register (CKCFG_LOCK_CFG)¶
Offset: 0x58
Reset value: 0x00,000,000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | CKCFG_LOCK | 0x0 | RW | When the software configures the PLL and clock gating related registers, you need to write 0x51AC0FFE to this register to unlock it, and then you can configure it and write any other value to lock it. Reading the value of this register has the following meanings: 1: this register is unlocked and can be written 0: this register is not unlocked and cannot be written. |
Frequency Division Parameter Register 0 (CLKDIV_PARAM0_CFG)¶
Offset: 0x80
Reset value: 0x1001808C
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31 | Reserved | 0x0 | RW | Reserved |
| 30:24 | TIMER_GPWM_DIV | 0x10 | RW | Clock division parameters of TIMER and PWM modules |
| 23:12 | ST_DIV | 0x18 | RW | Frequency division parameters of the CPU core tick clock |
| 11:9 | DTR_RAM_DIV | 0x0 | RW | Clock division parameters of RAM in DTR Flash module |
| 8:6 | DTR_DIV | 0x2 | RW | Clock division parameters of DTR Flash module |
| 5:0 | ADC_DIV | 0xC | RW | Clock division parameters of ADC module |
Frequency Division Parameter Register 1 (CLKDIV_PARAM1_CFG)¶
Offset: 0x84
Reset value: 0x00008208
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:12 | Reserved | 0x0 | RW | Reserved |
| 11:6 | UART1_DIV | 0x8 | RW | Clock division parameters of UART1 module |
| 5:0 | UART0_DIV | 0x8 | RW | Clock division parameters of UART0 module |
Frequency Division Parameter Enable Register (CLK_DIV_PARAM_EN_CFG)¶
Offset: 0xB0
Reset value: 0x00,000,000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:11 | Reserved | 0x0 | RW | Reserved |
| 10 | SRC2_MCLK_DIV_EN | 0x0 | RW | Frequency division parameter SRC2_MCLK_Update enable of DIV: 1: enable 0: disable |
| 9 | SRC1_MCLK_DIV_EN | 0x0 | RW | Frequency division parameter SRC1_MCLK_Update enable of DIV: 1: enable 0: disable |
| 8 | SRC0_MCLK_DIV_EN | 0x0 | RW | Frequency division parameter SRC0_MCLK_Update enable of DIV: 1: enable 0: disable |
| 7 | Reserved | 0x0 | RW | Reserved |
| 6 | UART1_DIV_EN | 0x0 | RW | Frequency division parameter UART1_Update enable of DIV: 1: enable 0: disable |
| 5 | UART0_DIV_EN | 0x0 | RW | Frequency division parameter UART0_Update enable of DIV: 1: enable 0: disable |
| 4 | TIMER_GPWM_DIV_EN | 0x0 | RW | Frequency division parameter TIMER_GPWM_Update enable of DIV: 1: enable 0: disable |
| 3 | ST_DIV_EN | 0x0 | RW | Frequency division parameter ST_Update enable of DIV: 1: enable 0: disable |
| 2 | DTR_RAM_DIV_EN | 0x0 | RW | Frequency division parameter DTR_RAM_Update enable of DIV: 1: enable 0: disable |
| 1 | DTR_DIV_EN | 0x0 | RW | Frequency division parameter DTR_Update enable of DIV: 1: enable 0: disable |
| 0 | Reserved | 0x0 | RW | Reserved |
System Clock Gating Configuration Register (SYS_CLKGATE_CFG0)¶
Offset: 0x11C
Reset value: 0x00000FFC
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:12 | Reserved | 0x0 | RW | Reserved |
| 11 | ROM_CKEN | 0x1 | RW | ROM module clock gating: 0: turn off the clock 1: turn on the clock |
| 10 | SRAM6_CLKEN | 0x1 | RW | Clock gating of SRAM6 module: 0: Turn off the clock 1: Turn on the clock |
| 9 | SRAM5_CLKEN | 0x1 | RW | Clock gating of SRAM5 module: 0: Turn off the clock 1: Turn on the clock |
| 8 | SRAM4_CLKEN | 0x1 | RW | Clock gating of SRAM4 module: 0: Turn off the clock 1: Turn on the clock |
| 7 | SRAM3_CLKEN | 0x1 | RW | Clock gating of SRAM3 module: 0: Turn off the clock 1: Turn on the clock |
| 6 | SRAM2_CLKEN | 0x1 | RW | Clock gating of SRAM2 module: 0: Turn off the clock 1: Turn on the clock |
| 5 | SRAM1_CLKEN | 0x1 | RW | Clock gating of SRAM1 module: 0: Turn off the clock 1: Turn on the clock |
| 4 | SRAM0_CLKEN | 0x1 | RW | SRAM0 module clock gating: 0: turn off the clock 1: turn on the clock |
| 3 | STCLK | 0x1 | RW | System tick clock STCLK module clock gating: 0: Turn off the clock 1: Turn on the clock |
| 2 | CPU_CORECLK | 0x1 | RW | Clock gating of CPU core clock module: 0: Turn off the clock 1: Turn on the clock |
| 1 | SLEEPDEEP | 0x0 | RW | Clock gating when the CPU is in deep sleep: 0: Turn off the clock 1: Turn on the clock |
| 0 | SLEEPING | 0x0 | RW | Clock gating during CPU sleep: 0: Turn off the clock 1: Turn on the clock |
Note 1: The above SRAM0 to SRAM6 together form 640KB SRAM in the chip. In normal use, please set all clocks to ON status
Note 2: The above deep sleep and sleep are two sleep modes of the CPU, which can be realized by directly writing the built-in registers of the CPU. When using this mode, you need to turn on the corresponding clock in advance. The user can refer to the relevant data of the CPU for setting
AHB Bus Module Clock Gating Configuration Register (AHB_CLKGATE_CFG)¶
Offset: 0x124
Reset value: 0x0000007F
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:5 | Reserved | 0x3 | RW | Reserved |
| 4 | DTR_CKEN | 0x1 | RW | Clock gating of DTR Flash module: 0: Turn off the clock 1: Turn on the clock |
| 3 | Reserved | 0x1 | RW | Reserved |
| 2 | Reserved | 0x1 | RW | Reserved |
| 1 | GDMA_CKEN | 0x1 | RW | Clock gating of DMA module: 0: Turn off the clock 1: Turn on the clock |
| 0 | Reserved | 0x1 | RW | Reserved |
APB0 Bus Module Clock Gating Configuration Register (APB0_CLKGATE_CFG)¶
Offset: 0x128
Reset value: 0x00007FFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:14 | Reserved | 0x3 | RW | Reserved |
| 13 | WWDG_CPU_HALT_CKEN | 0x1 | RW | Window watchdog WWDG module clock gating when CPU is in HALT state: 0: turn off the clock 1: turn on the clock |
| 12 | CODEC_DA_CKEN | 0x1 | RW | Clock gating of CODEC module DAC: 0: Turn off the clock 1: Turn on the clock |
| 11 | CODEC_AD_CKEN | 0x1 | RW | Clock gating of CODEC module ADC: 0: Turn off the clock 1: Turn on the clock |
| 10 | TIMER3_CKEN | 0x1 | RW | TIMER3 module clock gating: 0: turn off the clock 1: turn on the clock |
| 9 | TIMER2_CKEN | 0x1 | RW | TIMER2 module clock gating: 0: turn off the clock 1: turn on the clock |
| 8 | TIMER1_CKEN | 0x1 | RW | TIMER1 module clock gating: 0: turn off the clock 1: turn on the clock |
| 7 | TIMER0_CKEN | 0x1 | RW | TIMER0 module clock gating: 0: turn off the clock 1: turn on the clock |
| 6 | Reserved | 0x1 | RW | Reserved |
| 5 | GPWM2_CKEN | 0x1 | RW | Clock gating of PWM2 module: 0: Turn off the clock 1: Turn on the clock |
| 4 | GPWM1_CKEN | 0x1 | RW | Clock gating of PWM1 module: 0: Turn off the clock 1: Turn on the clock |
| 3 | GPWM0_CKEN | 0x1 | RW | Clock gating of PWM0 module: 0: Turn off the clock 1: Turn on the clock |
| 2 | Reserved | 0x1 | RW | Reserved |
| 1 | IIC_CKEN | 0x1 | RW | Clock gating of IIC module: 0: Turn off the clock 1: Turn on the clock |
| 0 | WWDG_CKEN | 0x1 | RW | Clock gating of WWDG module: 0: Turn off the clock 1: Turn on the clock |
APB1 Bus Module Clock Gating Configuration Register (APB1_CLKGATE_CFG)¶
Offset: 0x12C
Reset value: 0x000001FF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:9 | Reserved | 0x3 | RW | Reserved |
| 8:6 | Reserved | 0x7 | RW | Reserved |
| 5 | Reserved | 0x1 | RW | Reserved |
| 4 | Reserved | 0x1 | RW | Reserved |
| 3 | UART1_CKEN | 0x1 | RW | Clock gating of UART1 module: 0: Turn off the clock 1: Turn on the clock |
| 2 | UART0_CKEN | 0x1 | RW | Clock gating of UART0 module: 0: Turn off the clock 1: Turn on the clock |
| 1 | GPIO1_CKEN | 0x1 | RW | Clock gating of GPIO1 module: 0: Turn off the clock 1: Turn on the clock |
| 0 | GPIO0_CKEN | 0x1 | RW | Clock gating of GPIO0 module: 0: Turn off the clock 1: Turn on the clock |
SCU Status Register (SCU_STATE_REG)¶
Offset: 0x178
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:5 | Reserved | 0x0 | RW | Reserved |
| 4 | CPU_DEEPSLEEP | 0x0 | RW | CPU deep sleep status query: 0: not in deep sleep status 1: in deep sleep status |
| 3 | CPU_SLEEP | 0x0 | RW | CPU sleep status query: 0: not in sleep status 1: in sleep status |
| 2 | PLL_LOCK_STATE | 0x0 | RW | PLL lock status query: 0: not locked 1: locked |
| 1 | BOOT_MODE | 0x0 | RW | System startup mode query: 0: on-chip ROM startup 1: on-chip SRAM startup |
| 0 | Reserved | 0x1 | RW | Reserved |
AHB Bus Module Software Reset Configuration Register (AHB_RESET_CFG)¶
Offset: 0x190
Reset value: 0x0000007E
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:5 | Reserved | 0x3 | RW | Reserved |
| 4 | DTR_RSTEN | 0x1 | RW | DTR Flash module software reset control: 0: reset 1: no reset |
| 3 | Reserved | 0x1 | RW | Reserved |
| 2 | Reserved | 0x1 | RW | Reserved |
| 1 | GDMA_RSTEN | 0x1 | RW | DMA module software reset control: 0: reset 1: no reset |
| 0 | Reserved | 0x1 | RW | Reserved |
APB0 Bus Module Software Reset Configuration Register (APB0_RESET_CFG)¶
Offset: 0x194
Reset value: 0x00000FFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:12 | Reserved | 0x0 | RW | Reserved |
| 11 | TIMER23_RSTEN | 0x1 | RW | TIMER2 and TIMER3 module software reset control: 0: reset 1: no reset |
| 10 | Reserved | 0x1 | RW | Reserved |
| 9 | TIMER01_RSTEN | 0x1 | RW | TIMER0 and TIMER1 module software reset control: 0: reset 1: no reset |
| 8 | Reserved | 0x1 | RW | Reserved |
| 7 | GPWM23_RSTEN | 0x1 | RW | PWM2 module software reset control: 0: reset 1: no reset |
| 6 | Reserved | 0x1 | RW | Reserved |
| 5 | GPWM01_RSTEN | 0x1 | RW | PWM0 and PWM1 module software reset control: 0: reset 1: no reset |
| 4 | Reserved | 0x1 | RW | Reserved |
| 3 | CODEC_RSTEN | 0x1 | RW | CODEC module software reset control: 0: reset 1: no reset |
| 2 | Reserved | 0x1 | RW | Reserved |
| 1 | IIC_RSTEN | 0x1 | RW | IIC module software reset control: 0: reset 1: no reset |
| 0 | WWDG_RSTEN | 0x1 | RW | Window watchdog WWDG module software reset control: 0: reset 1: no reset |
APB1 Bus Module Software Reset Configuration Register (APB1_RESET_CFG)¶
Offset: 0x198
Reset value: 0x000001FF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:6 | Reserved | 0x0 | RW | Reserved |
| 5 | Reserved | 0x1 | RW | Reserved |
| 4 | Reserved | 0x1 | RW | Reserved |
| 3 | UART1_RSTEN | 0x1 | RW | UART1 module software reset control: 0: reset 1: no reset |
| 2 | UART0_RSTEN | 0x1 | RW | UART0 module software reset control: 0: reset 1: no reset |
| 1 | GPIO1_RSTEN | 0x1 | RW | GPIO1 module software reset control: 0: reset 1: no reset |
| 0 | GPIO0_RSTEN | 0x1 | RW | GPIO0 module software reset control: 0: reset 1: no reset |
Wake Up Mask Configuration Register (WAKEUP_MASK_CFG)¶
Offset: 0x1DC
Reset value: 0x00,000,000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:17 | Reserved | 0x0 | RW | Reserved |
| 16 | Reserved | 0x0 | RW | Reserved |
| 15 | Reserved | 0x0 | RW | Reserved |
| 14 | VDT_INT | 0x0 | RW | VDT module interrupt wake-up enable: 0: disable 1: enable |
| 13 | Reserved | 0x0 | RW | Reserved |
| 12 | Reserved | 0x0 | RW | Reserved |
| 11 | GPIO1_INT | 0x0 | RW | GPIO1 module interrupt wake-up enable: 0: disable 1: enable |
| 10 | GPIO0_INT | 0x0 | RW | GPIO0 module interrupt wake-up enable: 0: disable 1: enable |
| 9 | Reserved | 0x0 | RW | Reserved |
| 8 | UART1_INT | 0x0 | RW | UART1 module interrupt wake-up enable: 0: disable 1: enable |
| 7 | UART0_INT | 0x0 | RW | UART0 module interrupt wake-up enable: 0: disable 1: enable |
| 6 | TIMER1_INT | 0x0 | RW | TIMER1 module interrupt wake-up enable: 0: disable 1: enable |
| 5 | TIMER0_INT | 0x0 | RW | TIMER0 module interrupt wake-up enable: 0: disable 1: enable |
| 4 | WWDG_INT | 0x0 | RW | Window watchdog WWDG module interrupt wake-up enable: 0: disable 1: enable |
| 3 | IWDG_INT | 0x0 | RW | Independent watchdog IWDG module interrupt wake-up enable: 0: disable 1: enable |
| 2 | Reserved | 0x0 | RW | Reserved |
| 1 | Reserved | 0x0 | RW | Reserved |
| 0 | SCU_INT | 0x0 | RW | SCU module interrupt wake-up enable: 0: disable 1: enable |
Interrupt Status Register (INT_STATE_REG)¶
Offset: 0x1F4
Reset value: 0x00,000,000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:17 | Reserved | 0x0 | W1C | Reserved |
| 16 | Reserved | 0x0 | W1C | Reserved |
| 15 | Reserved | 0x0 | W1C | Reserved |
| 14 | Reserved | 0x0 | W1C | Reserved |
| 13 | Reserved | 0x0 | W1C | Reserved |
| 12 | Reserved | 0x0 | W1C | Reserved |
| 11 | GPIO1_INT_WAKE | 0x0 | W1C | GPIO1 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 10 | GPIO0_INT_WAKE | 0x0 | W1C | GPIO0 Module Interruption Wakeup Status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 9 | Reserved | 0x0 | W1C | Reserved |
| 8 | UART1_INT_WAKE | 0x0 | W1C | UART1 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 7 | UART0_INT_WAKE | 0x0 | W1C | UART0 module interrupt Wake up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 6 | TIMER1_INT_WAKE | 0x0 | W1C | TIMER1 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 5 | TIMER0_INT_WAKE | 0x0 | W1C | TIMER0 Module Interruption Wakeup Status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 4 | WWDG_INT_WAKE | 0x0 | W1C | Window watchdog WWDG module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 3 | IWDG_INT_WAKE | 0x0 | W1C | Independent watchdog IWDG module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 2 | Reserved | 0x0 | W1C | Reserved |
| 1 | Reserved | 0x0 | W1C | Reserved |
| 0 | SCU_INT_WAKE | 0x0 | W1C | SCU module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |