General Purpose Input Output (GPIO)

Introduction

GPIO (General Purpose IO Port) Each GPIO port has a corresponding control register and configuration register. API can be divided into two categories: one is to operate a pin independently, and the other is to operate one or more pins at the same time. Provide IO input/output status query interface, interrupt mask interface, interrupt mask query interface, interrupt clearing interface, interrupt status query interface, interrupt trigger mode configuration interface (configurable as: low-level trigger, high-level trigger, rising edge trigger, falling edge trigger, bilateral edge trigger), etc. to meet the requirements of different applications. CI130X chip now has 4 groups of GPIO: PA, PB, PC and PD, and each group of GPIO: PA, PB and PC has a pin_ 0 ~ pin_ 7. Each group of PD GPIO has pin_ 0 ~ pin_ 5.

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API

-The following APIs can set one or more PINs at the same time

Function name	Description
gpio_ set_ output_ Mode	GPIO device output mode configuration
gpio_ set_ input_ Mode	GPIO device input mode configuration
gpio_ get_ direction_ Status	GPIO device obtains IO direction
gpio_ irq_ Mask	GPIO device interrupt mask
gpio_ irq_ Unmask	The GPIO device cancels the interrupt mask
gpio_ irq_ trigger_ Config	The GPIO device sets the interrupt trigger mode
gpio_ set_ output_ high_ Level	GPIO device output high level
gpio_ set_ output_ low_ Level	GPIO device output low level
gpio_ get_ input_ Level	GPIO device acquisition input level

-The following APIs are used to set a PIN separately

Function name	Description
gpio_ get_ direction_ status_ Single	GPIO device obtains a pin input/output direction
gpio_ get_ irq_ raw_ status_ Single	The GPIO device obtains the status before a pin interrupt mask
gpio_ get_ irq_ mask_ status_ Single	The GPIO device obtains the status after a pin interrupt mask
gpio_ clear_ irq_ Single	GPIO device controls a pin clearing interrupt
gpio_ set_ output_ level_ Single	GPIO device controls one pin output
gpio_ get_ input_ level_ Single	GPIO device obtains a pin input

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Example

The following code controls the pin4 output mode of the PB group

scu_ set_ device_ gate((unsigned int)PB,ENABLE);        // Turn on PB clock
dpmu_ set_ io_ reuse(PB4,FIRST_FUNCTION);               // Set pin function reuse to GPIO
dpmu_ set_ io_ direction(PB4,DPMU_IO_DIRECTION_OUTPUT); // Set pin function to output mode
dpmu_ set_ io_ pull(PB4,DPMU_IO_PULL_DISABLE);          // Set Close Up and Down
gpio_ set_ output_ mode(PB,pin_4);                      // GPIO pin is configured as output mode
gpio_ set_ output_ level_ single(PB,pin_4,0);            // Output low level
gpio_ set_ output_ level_ single(PB,pin_4,1);            // Output high level

The following code configures pin4 of PB group as open drain output mode

scu_ set_ device_ gate((unsigned int)PB,ENABLE);       // Turn on PB clock
dpmu_ set_ io_ reuse(PB4,FIRST_FUNCTION);              // Set pin function reuse to GPIO
dpmu_ set_ io_ open_ drain(PB4,ENABLE);                 // Configure pin leakage opening function, support external pull-up 5V
dpmu_ set_ io_ pull(PB4,DPMU_IO_PULL_DISABLE);         // Close pull-up
dpmu_ set_ io_ direction(PB4,DPMU_IO_DIRECTION_OUTPUT);// Set pin function to output mode
gpio_ set_ output_ mode(PB,pin_4);                     // GPIO pin is configured as output mode

The following code configures IIC port (PB7/PC0) as open drain output mode

dpmu_ set_ io_ reuse(PB7,THIRD_FUNCTION);  // Set pin function reuse to IIC
dpmu_ set_ io_ reuse(PC0,THIRD_FUNCTION);  // Set pin function reuse to IIC
dpmu_ set_ io_ open_ drain(PB7,ENABLE);      // Configure pin leakage opening function, support external pull-up 5V
dpmu_ set_ io_ open_ drain(PC0,ENABLE);      // Configure pin leakage opening function, support external pull-up 5V
dpmu_ set_ io_ pull(PB7,DPMU_IO_PULL_DISABLE);   // Close pull-up
dpmu_ set_ io_ pull(PC0,DPMU_IO_PULL_DISABLE);   // Close pull-up
dpmu_ set_ io_ direction(PC0,DPMU_IO_DIRECTION_OUTPUT);  // SCL configured as output

The following code configures pin4 of the PB group as the input mode

scu_ set_ device_ gate((unsigned int)PB,ENABLE);       // Turn on PB clock
dpmu_ set_ io_ reuse(PB4,FIRST_FUNCTION);              // Set pin function reuse to GPIO
dpmu_ set_ io_ direction(PB4,DPMU_IO_DIRECTION_INPUT); // Set pin function to input mode
dpmu_ set_ io_ pull(PB4,DPMU_IO_PULL_DISABLE);         // Set Close Up and Down
gpio_ set_ input_ mode(PB,pin_4);                      // GPIO pin is configured as input mode
If (0==gpio_get_input_level_single (PB, pin_4))//Get the IO status
{
//INFO: input is low level
}
else
{
//INFO: input is high level
}

The following code configures the interrupt of pin 4 of PB group as double edge trigger

scu_ set_ device_ gate((unsigned int)PB,ENABLE);            // Turn on PB clock
dpmu_ set_ io_ reuse(PB4,FIRST_FUNCTION);                   // Set pin function reuse to GPIO
dpmu_ set_ io_ direction(PB4,DPMU_IO_DIRECTION_INPUT);    // Set pin function to input mode
dpmu_ set_ io_ pull(PB4,DPMU_IO_PULL_DISABLE);            // Set Close Up and Down
gpio_ set_ input_ mode(PB,pin_4);                         // GPIO pin is configured as input mode
gpio_ irq_ trigger_ config(PB,pin_4,both_edges_trigger);  // Interrupt trigger mode
eclic_ irq_ enable(PB_IRQn);    // Enable interrupt

Warning

PA, PB and PC have input, output and interrupt functions, PD only has input and output functions, without interruption.