IIC¶
Function introduction¶
IICC (Inter IC Controller, IIC bus controller) is built in the chip, which supports standard transmission mode rate of 100Kbit/s and fast transmission mode rate of 400Kbit/s. Its main characteristics are as follows:
- Support IIC Master mode, and support 7-bit and 10 bit addressing in master mode
- Support IIC transmitter and receiver functions
- IIC bus speed is configurable, and supports Standard-100Kbps/Fast-400Kbps
- Support multi master bus arbitration function
- Support SCL bus clock synchronization and handshaking
- Support interrupt and query operation mode
Register Mapping¶
The base address of IIC register mapping is 0x40011000. See Table IIC-1 for detailed register mapping.
Table IIC-1 IIC Register Mapping
| Offset | Name | Bit Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| 0x00 | IIC_ SCLDIV | 32 | R/W | 0x00FA00FA | IIC SCL frequency division parameter register |
| 0x04 | IIC_ SRHLD | 32 | R/W | 0x00FA00FA | IIC Start condition hold time |
| 0x08 | IIC_ DTHLD | 32 | R/W | 0x00040004 | IIC SDA Data time |
| 0x0C | IIC_ GLBCTRL | 32 | R/W | 0x00040080 | IIC global control register |
| 0x10 | IIC_ CMD | 32 | R/W | 0x00000000 | IIC command register |
| 0x14 | IIC_ INTEN | 32 | R/W | 0x00000000 | IIC interrupt enable control register |
| 0x18 | IIC_ INTCLR | 32 | WO | 0x00000000 | IIC interrupt clear register |
| 0x20 | IIC_ TXDR | 32 | R/W | 0x00000000 | IIC sending data register |
| 0x24 | IIC_ RXDR | 32 | RO | 0x00,000,000 | IIC receive data register |
| 0x28 | IIC_ TIMEOUT | 32 | R/W | 0x05F5E100 | IIC Timeout register |
| 0x2C | IIC_ STATUS | 32 | RO | 0x00001004 | IIC status register |
SCL frequency division parameter register (IIC_SCLDIV)¶
Offset: 0x00
Reset value: 0x00FA00FA
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:16 | IIC_ SCLHWID | 0x00FA | R/W | SCL high-level width. Only the master is valid. Count with PCLK as the clock. By default, 5us is set at 50MHz-100Kbps. |
| 15:0 | IIC_ SCLWID | 0x00FA | R/W | SCL low level width. Count with PCLK as the clock. By default, 5us is set at 50MHz-100Kbps 1. Master is used to generate SCL clock 2. After data transmission, the hardware will automatically pull down the SCL until TB is high. When TB is high, the hardware will continue to pull down the SCL for the time set in this register, and then output the SCL high level to ensure that the data is stable at the SCL high level. |
START/STOP HOLD TIME register (IIC_SRHLD)¶
Offset: 0x04
Reset value: 0x00FA00FA
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:16 | IIC_ SPHLD | 0x00FA | R/W | The hold time of the stop condition (that is, the time from the stop condition to the confirmed idle state). It is counted by the PCLK clock. Only the master is valid. The default is 50MHz-100kbps, 5us. |
| 15:0 | IIC_ SRHLD | 0x00FA | R/W | The hold time of the Start/repeat start condition, which is counted by the PCLK clock. Only the master is valid. The default is 50MHz-100kbps, 5us. |
DATA Sample/HOLD TIME register (IIC_DHLD)¶
Offset: 0x08
Reset value: 0x00040004
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:16 | IIC_ DTSAMPLE | 0x0004 | R/W | The SDA signal is sampled after this configured time interval after the rising edge of the SCL. Since SDA is effective at the high level of SCL, this register is set to control the sampling time and sample data at the rising edge of SCL as soon as possible. |
| 15:0 | IIC_ DHLD | 0x0004 | R/W | Data hold time. As a transmitter, wait for this time before sending a new SDA to the bus when the falling edge of SCL occurs. Data is sent at the falling edge of the fastest SCL. |
Global control register (IIC_GLBCTRL)¶
Offset: 0x0C
Reset value: 0x00040080
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:24 | Reserved | 0x00 | R/W | Reserved |
| 23:16 | BUS_ FILTWID | 0x04 | R/W | I2C bus signal filtering width, which supports SCL and SDA filtering of 256 PCLK cycles at most. |
| 7 | SW_ RSTn | 0x1 | R/W | Soft reset of the module, effective when low. Write 0 first and then write 1 to complete the reset. |
| 3 | TIMEOUT_ EN | 0 | R/W | Timeout function enable, highly effective. |
| 2 | Reversed | 0 | R/W | Reserved |
| 1 | GLB_ EN | 0 | R/W | The module is globally enabled and highly effective. |
| 0 | MSTSLV | 0 | R/W | Master mode selection 0: Reserved 1: Master mode. The software cannot enter the master mode until the I2C bus is in the IDLE state. |
Command register (IIC_CMD)¶
Offset: 0x10
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:5 | Reserved | 0x00000000 | R/W | Reserved |
| 4 | START | 0 | R/W | The start/re start condition is generated. It is valid only in the master mode. This command cannot be issued until the I2C bus IDLE. The hardware will be reset automatically after the Start condition is generated 0: no start condition is generated 1: Generate the start condition. |
| 3 | STOP | 0 | R/W | A stop condition is generated. It is only valid for the master. After the stop condition is generated, the hardware will be reset automatically 0: no stop condition is generated 1: A stop condition is generated. |
| 2 | ACK | 0 | R/W | When used as a receiver, the response control to the transmitter after the current byte data is transmitted. The software needs to configure the ACK of the next byte data when reading the currently received 1-byte data 0: send ACK to transmitter 1: Send NOACK to transmitter. |
| 0 | TB | 0 | R/W | The command configuration is valid 0: After 1byte data transmission, the hardware automatically clears to zero, indicating that the value in the command register is invalid, that is, the data transmission is completed and waits for the CPU to respond 1: The command register configuration is valid for new data transmission. |
Interrupt enable control register (IIC_INTEN)¶
Offset: 0x14
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:7 | Reserved | 0x00000000 | R/W | Reserved |
| 6 | SLVADIE | 0 | R/W | The slave address is enabled by the hit interrupt 0: disable this interrupt 1: Interrupt the CPU when the slave is found or there is a general call. |
| 5 | ARBLSTIE | 0 | R/W | Arbitration loss interrupt enable 0: arbitration loss interrupt generation is prohibited 1: Master mode interrupts the CPU when arbitration loses bus control. |
| 4 | SSTOPIE | 0 | R/W | Stop condition detection interrupt 0: Stop condition detection interrupt generation is prohibited 1: slave mode interrupts the CPU when a stop condition is detected. |
| 3 | BEIE | 0 | R/W | Bus error interrupt enable 0: disable the interrupt 1: Interrupt the CPU when a bus error occurs. The start/stop condition generated during 1Byte data+ACK is regarded as a bus error. |
| 2 | TXDEPTIE | 0 | R/W | Enable air interrupt of the sending register 0: disable the interrupt 1: An interrupt is generated to the CPU after 1-byte data transmission (including the ACK bit) is completed. |
| 1 | RXDFULIE | 0 | R/W | Receive register full interrupt enable 0: disable the interrupt 1: When 1-byte data reception (including ACK bit) is completed, an interrupt is generated to the CPU and the CPU is notified to read the data. |
| 0 | TIMEOUTIE | 0 | R/W | Timeout interrupt enable 0: This interrupt is not allowed 1: When the bus high/low level duration between start and stop exceeds the preset value, a timeout interrupt is generated to the CPU, which handles the behavior of this module. |
Interrupt/Status Clear Register (IIC_INTCLR)¶
Offset: 0x18
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:7 | Reserved | 0x00000000 | W | Reserved |
| 6 | CLR_ SLVAD | 0 | W | When writing 1 to this bit, clear the slaved/general call status/interrupt. |
| 5 | CLR_ ARBLST | 0 | W | Clear arbitration loss status/interrupt when writing 1 to this bit. |
| 4 | CLR_ SSTOP | 0 | W | When writing 1 to this bit, the clear slave detects the stop condition status/interrupt. |
| 3 | CLR_ BE | 0 | W | Clear the bus error status/interrupt when writing 1 to this bit. |
| 2 | CLR_ TXDEPT | 0 | W | When writing 1 to this bit, clear the send data register null status/interrupt. |
| 1 | CLR_ RXDFUL | 0 | W | When writing 1 to this bit, clear the receive data register full status/interrupt. |
| 0 | CLR_ TIMEOUT | 0 | W | Clear timeout status/interrupt when writing 1 to this bit. |
Send Data Register (IIC_TXDR)¶
Offset: 0x20
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:8 | Reserved | 0x00,000,000 | R/W | Reserved |
| 7:0 | IIC_ TXDR | 0 | R/W | Data to be sent to IIC bus [0]: the R/NW bit is used after the start of the master, and the lowest bit of the data is used in other times [7:1]: When the master is started, it is used as the slave address to be addressed, and the rest is used as [7:1] of the data. |
Receive Data Register (IIC_RXDR)¶
Offset: 0x24
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:8 | Reserved | 0x00000000 | R | Reserved |
| 7:0 | IIC_ RXDR | 0 | R | Data received from IIC bus |
Bus TIMEOUT register (IIC_TIMEOUT)¶
Offset: 0x28
Reset value: 0x05F5E100
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | TIMEOUT_ VALUE | 0x05F5E100 | R/W | Timeout preset value. When the bus SCL high level exceeds this setting, timeout occurs, and PCLK is used as the reference clock for counting. |
Status register (IIC_STATUS)¶
Offset: 0x2C
Reset value: 0x00001004
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:16 | Reserved | 0x0000 | R | Reserved |
| 15 | I2CBUS_ BUSY | 0 | R | I2C bus IDLE/BUSY status 0: I2C bus is in IDLE state 1: I2C bus is in busy state, which is high between start and stop conditions. |
| 14 | ACK_ STAT | 0 | R | Response status of ACK cycle 0: The receiver sends an ACK to the transmitter 1: The receiver sends a NOACK to the transmitter. |
| 13 | REWR | 0 | R | Read/write status. It is the R/NW bit after the slave address. It is automatically reset after stop 0: This module acts as a master transmitter or slave receiver 1: This module acts as a master receiver or slave transmitter. |
| 12 | TBCMPLT | 1 | R | 1byte data transmission completion status, in IIC_ When CMD [TB] is valid, it will be reset automatically 0: data transmission (sending/receiving) of 1 byte is not completed 1: complete data transmission (sending/receiving) of one byte; |
| 11 | TRANSMITTER | 0 | R | Transmitter flag. The internal logic automatically generates the transmitter flag according to the R/nW bits on the bus and the master/slave mode. The flag is cleared automatically after the stop 1: This module acts as the master/slave transmitter 0: This module acts as the master/slave receiver; |
| 10 | MST_ SLV | 0 | R | The master/slave mode status of the current module. Due to bus contention, the module may not work in the master mode 1: This module works in master mode 0: This module works in slave mode. |
| 9: 8 | Reserved | 0 | R | Reserved |
| 7 | GENCALL | 0 | R | Broadcast call detection status 0: No broadcast call 1: There are broadcast calls on the bus. |
| 6 | SLVAD | 0 | R | Slave is found 0: This slave is not found 1: This slave is found by other masters on the bus. |
| 5 | ARBLST | 0 | R | Master bus arbitration loss status 0: The bus arbitration is not lost 1: The bus arbitration lost the bus control right. |
| 4 | SSTOP | 0 | R | Stop condition detection status. Both master and slave can be used 0: no stop condition occurs on the bus 1: The bus has a stop condition. |
| 3 | BERR | 0 | R | Bus error status 0: the bus is normal 1: An error occurred on the bus, and the IIC protocol was violated. |
| 2 | TXDEPT | 1 | R | 1 byte data status after sending 0: 1byte data has not been sent completely 1: 1 byte of data has been sent. |
| 1 | RXDFUL | 0 | R | Status of receiving 1byte data 0: data receiving register is empty 1: The data receiving register is full. |
| 0 | TIMEOUT | 0 | R | Timeout status 0: no timeout 1: Timeout occurs when the SCL high level width exceeds the preset value. |