Skip to content

Hardware Design

The periphery of CI1306 chip only needs a few devices to support various voice applications. For the voice part, the chip can support the scheme of dual microphone input or single microphone input+AEC echo cancellation. The user can select the appropriate circuit according to the function, power consumption and cost requirements of the designed application scheme. The following describes the application reference circuit diagram of a single microphone input+AEC echo cancellation scheme of the chip.

Application reference circuit diagram

The application reference circuit diagram is shown in Figure H-1. It is the circuit diagram of a CI1306 application scheme that supports single microphone input+AEC echo cancellation and power amplifier output.

单麦本地语音识别应用系统图

Figure H-1 CI1306 Application Reference Circuit Diagram

The chip can use 5V direct power supply, and users can design according to the corresponding peripheral device specifications in the figure above.

If the board level online upgrade function is to be considered during schematic design, the UART0 pin can be led out to facilitate the firmware upgrade of the flash in the main chip through UART0 after the PCB board placement is completed. The PA4 (PG_EN) pin of the chip is internally pulled up. The power on defaults to the upgrade mode. After power on, the upgrade signal sent from the external UART0 port should be detected. If there is one, the upgrade should be started directly. The default boot time of the chip is extended by adding detection of upgrade mode, about 850mS; If the user has high requirements for the power on time, you can lead out the PA4 pin, add two 2.2K Ω pull-down resistors to the ground, and add a test point between the two 2.2K resistors. At this time, the chip is powered on in the normal mode, and the power on time is about 350mS, which can shorten the power on time. If you want to upgrade online at this time, you can externally supply high level to the intermediate test points connected by two 2.2K Ω resistors, pull up the PA4 pin, and then upgrade through UART0.

The chip scheme can select differential microphone design or single ended microphone design, and the differential microphone design in the above figure is recommended. If the user has requirements for cost, the microphone part in the above figure can be modified to a single ended microphone design, which can use fewer passive devices than the differential microphone. However, this method is only recommended for applications where the microphone line length is less than 20 cm, otherwise the speech recognition effect will not be as good as the differential microphone design because the line length is too long and the anti-interference effect is not enough. The power amplifier in the above figure is of class AB, and 8002 power amplifier chip is recommended. Users can also choose the power amplifier chip according to the requirements of the scheme. If the power amplifier function is not required, this part of the circuit can also be removed to reduce the cost. If users do not use AEC echo cancellation function, they can also remove this part of the circuit to reduce costs.

If the user has no special requirements for the power consumption of the scheme, it is recommended to directly use the PMU inside the chip for power supply. If there is a power consumption requirement, the external DCDC chip can be added to power the chip 1.1V to reduce the power consumption. All UART ports of the chip support 5V communication. The UART0 port in the above figure is a 3.3V signal. If 5V is to be connected, add a pull-up resistor connected to 5V around the RX and TX pins of UART0. No additional voltage conversion circuit is required.

Chipintelli provides a variety of scheme reference schematics, which can meet most common application scenarios. In the actual application development, the customer needs to carefully select one of the most suitable reference schematics for reference and design optimization according to the specific product functional performance requirements, system characteristics and application scenarios. As Chipintelli is unable to master all product systems and application knowledge, customers or solution partners are expected to fully test and verify product functional performance (including the matching of voice chips and modules with product systems) in combination with product systems and application scenarios before mass production. If there are unclear and uncertain problems during the design modification process, please contact Chipintelli FAE engineer for full communication. Users can refer to the following documents:

Scheme name Scheme function Scheme application scenario Document center link
Typical scheme Single microphone differential microphone input with echo cancellation function Suitable for widely used products, products with broadcasting and echo cancellation Reference schematic diagram for typical scheme
Dual microphone AEC scheme Dual microphone differential microphone input with echo cancellation function Products with dual microphone input and echo cancellation requirements Reference schematic diagram of dual microphone AEC scheme

The schematic source document and PCB reference can be found in the ☞Chipintelli Speech AI Development Platform.

PCB Layout Design

Power circuit

  1. Power wiring Attention shall be paid to overvoltage and surge protection for power input. TVS devices and 4.7 ohm resistors shall be designed for 5V input. The wiring shall pass through TVS first, and then through resistors to the chip. The power supply wiring diameter depends on the actual circuit current. The wiring width of 3.3V power supply is not less than 15ml, and that of 1.2V power supply is not less than 15ml. Copper clad wiring shall be used as far as possible. The power supply wiring shall be as short and thick as possible. The narrowest part of the power supply wiring shall not be less than 8mil line width to avoid the power supply wiring forming a closed loop.

  2. Power decoupling capacitor The power decoupling capacitor is arranged close to the corresponding pin.

Electrostatic protection requirements

In the design of two-layer boards, try to route in the TOP layer to maintain the integrity of the BOTTOM ground plane. If ESD devices are designed, try to close the ESD devices to the pins of the plug-in to improve the protection effect.

Other considerations for application

  1. It is recommended to directly use external crystal oscillator for CI1306 chip scheme. If the user has high requirements for cost, but has no requirements for the size and accuracy of the chip’s main frequency and the temperature range of the working environment, the RC oscillator built in the chip can be used. However, please note that the RC oscillator built in the chip will have a certain temperature drift in high and low temperature environments due to the semiconductor technology principle. Please reduce the system’s main frequency to below 220MHz when using it. If the working environment temperature of the application needs - 40 to 85 ℃, please use an external crystal oscillator.
  2. If the operating temperature range of the application scenario is - 10 to 70 ℃, and only low-speed serial communication is conducted with the upper computer (baud rate is less than or equal to 115200bps), this kind of circuit scheme can directly use the RC oscillator built in the chip (the frequency offset of the upper computer is ≤± 1.5%). When the upper computer is designed without crystal oscillator, the communication error should be minimized. Chipintelli can provide a serial port baud rate adaptive scheme, which requires adding a handshake command to the serial port protocol, and the upper computer ensures that it will reply according to the protocol requirements within 50ms after receiving the handshake command. After adding this adaptive scheme, the product can be used in scenarios where the working environment temperature is - 20 to 85 ℃.
  3. The chip is integrated with a PMU management unit. The PMU contains three LDOs, which provide 3.3V and 1.1V voltage respectively for the chip. If there is no special requirement for power consumption, the scheme does not require an external power supply chip, and the ripple of the external 5V power supply must be less than 300mV.
  4. The chip is manufactured by lead-free environmental protection process. Please set furnace temperature, time and other parameters according to lead-free standard during SMT welding.
  5. Pay attention to the influence of static electricity when taking and packaging chips. It is recommended to use anti-static materials for isolation.