DTR Flash¶
The chip is equipped with a built-in Nor Flash controller that supports DTR, single wire and four wire operation, and can support various types of Nor Flash devices. The chip has built-in Nor Flash. When using it, users can directly call the corresponding driver code in the SDK to achieve Flash flashing, writing, reading and other functions.
Function Introduction¶
The main features of DMA controller are as follows:
- Data bus interface:
- Support BIT/HALF-WORD/WORD read/write operations
- Support SINGLE/BURST4/BURST8/BUSRT16 operations
- SPI interface:
- Support 4-wire SPI
- Support SPI (single line)/OCTAL (4-line)/DTR (4-line double edge) transmission modes
- Compatible with various FLASH command operations
- Support phase adjustment of transmission operation
- Support acquisition clock phase adjustment and delayline fine adjustment during data acquisition
- Data collection in DQS mode is supported
- Three controller operation modes:
- Prefetch read operation mode (XIP)
- General operating mode
- Transmit support register or FIFO buffer
- One read operation asynchronous FIFO, data width 32BIT, depth 64, trigger threshold configurable
- One write operation asynchronous FIFO, data width 32BIT, depth 64, trigger threshold configurable
- Two 32BIT data configuration registers
- Two 32BIT data reading registers
- Supported interrupt types:
- Universal operation mode completion flag interrupt source
- Bad write interrupt source
- FIFO underflow overflow interrupt source
- Operation interrupt source during reset
- Support DMA transmission
Register Mapping¶
The register mapping base address of the DTR Flash controller is 0x40004000. See Table F-1 for details.
Table F-1 DTR Flash Register Mapping
| Offset | Name | Bit Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| 0x00 | GLOBE_CFG | 32 | R/W | 0x00000000 | Global configuration register |
| 0x04 | GLOBE1_CFG | 32 | R/W | 0x00000000 | Global configuration register 1 |
| 0x08 | RX_CLK_CFG | 32 | R/W | 0x000000010 | Receive clock configuration register |
| 0x0C | ADDR_MASK_CFG | 32 | R/W | 0x00000FFF | Address mask configuration register |
| 0x10 | GM_CFG | 32 | R/W | 0x00000000 | General mode configuration register |
| 0x14 | GM1_CFG | 32 | R/W | 0x00000000 | General mode configuration register 1 |
| 0x18 | GM_ADDR_CFG | 32 | R/W | 0x00000000 | General mode read/write address configuration register |
| 0x1C | GM_DATA_SIZE_CFG | 32 | R/W | 0x00000000 | General mode data size configuration register |
| 0x20 | RD_CFG | 32 | R/W | 0x00000000 | Prefetch read mode configuration register |
| 0x24 | RD1_CFG | 32 | R/W | 0x00,000,000 | Prefetch read mode configuration register 1 |
| 0x30 | FIFO_LEVEL_CFG | 32 | R/W | 0x00000000 | FIFO level configuration register |
| 0x34 | R/W_DATA0_CFG | 32 | R/W | 0x00000000 | Read/write cache register 0 |
| 0x38 | R/W_DATA1_CFG | 32 | R/W | 0x00000000 | Read/write cache register 1 |
| 0x3C | INT_CTRL_CFG | 32 | R/W | 0x00000000 | Interrupt control configuration register |
| 0x40 | STATE_REG | 32 | R/W | 0x00000040 | Status register |
Global Configuration Register (GLOBE_CFG)¶
Offset: 0x000
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:14 | Reserved | 0 | R/W | Reserved |
| 13 | flash_clk_bypass | 0x0 | R/W | Flash device clock bypass enables the controller core Flash to use the same external clock, which is configured as 1. Tx is required to enable this function_data_shift sends the data phase to 0, rx_nege_en and rx_nege_sampleis configured as 1. |
| 12 | dpm_en | 0x0 | R/W | Enable the dpm mode sent, and the configuration is 1 |
| 11 | dtr_tx_nege_en | 0x0 | R/W | In DTR mode, the phase adjustment of sending data clock falling edge is valid when the configuration is 1 |
| 10:8 | dtr_tx_data_shift | 0x0 | R/W | Number of cycles of clock phase shift of transmitted data in DTR mode |
| 7 | dtr_tx_nege_en | 0x0 | R/W | In normal mode, the phase adjustment of sending data clock falling edge is valid when the configuration is 1 |
| 6:4 | dtr_tx_data_shift | 0x0 | R/W | Number of cycles of clock phase shift for sending data in normal mode |
| 3:2 | ram_clk_Md | 0x0 | R/W | Frequency relationship between fifo flash side clock and internal sram clock: 0: same frequency 1:2 frequency division 2:4 frequency division |
| 1:0 | flash_clk_div | 0x0 | R/W | Flash device clock frequency: 0: 2 division of the kernel clock 1: 4 division of the kernel clock 2: 6 division of the kernel clock 3: 8 division of the kernel clock |
Global Configuration Register 1 (GLOBE1_CFG)¶
Offset: 0x004
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:11 | Reserved | 0 | R/W | Reserved |
| 10 | flash_R/Wdata_maxnum_en | 0x0 | R/W | Single transmission limit enable, valid if 1 is configured |
| 9:2 | flash_R/Wdata_maxnum | 0x0 | R/W | The maximum number of read/write data in a single transmission. The value is the configured value of this register plus 1 Word |
| 1 | flash_hw_reset | 0x0 | R/W | flash hardware reset, valid if the configuration is 1 |
| 0 | ecc_dect_en | 0x0 | R/W | ECC signal detection enable, valid when configured as 1 |
Receive Clock Configuration Register (RX_CLK_CFG)¶
Offset: 0x08
Reset value: 0x00000010
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:22 | Reserved | 0 | R/W | Reserved |
| 21 | rx_nege_sample | 0x0 | R/W | In non DTR mode, the receiving clock uses falling edge sampling, and the configuration is 1 |
| 20 | rx_dqs_en | 0x0 | R/W | The external dps signal is selected for the receiving clock, and the configuration is valid as 1 |
| 19:4 | rx_clk_delay_sel | 0x1 | R/W | delay_Line Selection: [19] RX_CLK time domain, rx_Wptr phase selection 0x0: falling edge sampling 0x1: rising edge sampling [18] RX_CLK time domain, rx_Wptr output selection 0x0: raw rx_Wptr output 0x1: phase adjustment rx_Wptr output [17] core_Clk time domain, rx_Wptr phase selection 0x0: falling edge sampling 0x1: rising edge sampling [16] core_Clk time domain, rx_Wptr output selection 0x0: raw rx_Wptr output 0x1: phase adjustment rx_Wptr output [15:12] reserved [11:4] delay_Series range of line (1-32) |
| 3 | rx_nege_en | 0x0 | R/W | Enable the phase adjustment of the falling edge of the receiving clock, and the configuration is 1 |
| 2:0 | rx_clk_shift | 0x0 | R/W | Number of cycles of receiving clock phase shift |
Address Mask Configuration Register (ADDR_MASK_CFG)¶
Offset: 0x0C
Reset value: 0x00000FFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:12 | Reserved | 0 | R/W | Reserved |
| 11:0 | addr_mask | 0xFFF | R/W | Configure address masking. By default, the low 16bit address bit (15:0) of Flash is valid. Each bit of this register sequentially corresponds to the corresponding bit of the 16th bit address of Flash. For example, bit0 corresponds to the 16th bit of the Flash address. Writing 1 to this bit is masked, and 0 is unshielded. Example: The device size is 2MB, and the effective address of the device is 21 bits in total, addr_mask = 0xFE0； The device size is 4MB, and the effective address of the device is 22 bits in total, addr_mask = 0xFC0； The device size is 16MB, and the effective address of the device is 24 bits in total, ddr_mask = 0xF00； The device size is 32MB, and the effective address of the device is 25 bits in total, addr_mask = 0xE00. |
General Mode Configuration Register (GM_CFG)¶
Offset: 0x10
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:29 | Reserved | 0 | R/W | Reserved |
| 28:24 | gm_dummy_cycle | 0x0 | R/W | Number of cycles Dummy waits for flash |
| 23 | gm_data_store_Md | 0x0 | R/W | Storage method of read/write data: 0: fifo 1: rw_data_reg (dma mode is not supported) |
| 22 | gm_dma_wreq_Md | 0x0 | R/W | DMA write request sending method: 0: send write request when writing fifo amempty (fast empty status) 1: send write request when writing fifo empty (empty status) |
| 21 | gm_dma_en | 0x0 | R/W | DMA mode enable, valid if 1 is configured |
| 20 | Reserved | 0x0 | R/W | Reserved |
| 19 | gm_crm_en | 0x0 | R/W | Continuous read mode is enabled, and the configuration is 1 |
| 18:15 | gm_data_md_sel | 0x0 | R/W | Mode selection for reading and writing data: 4’b0000: single line mode 4’b0001: 4-line mode 4’b0100: single line merge mode 4’b0101: 4-line merge mode 4’b1000: DTR single line mode 4’b1001: DTR4 line mode 4’b1100: DTR single line merge mode 4’b1101: DTR4 line merge mode Others: Reverd |
| 14 | gm_write_en | 0x0 | R/W | Write data enable, valid if 1 is configured |
| 13 | gm_read_en | 0x0 | R/W | Read data enable, valid if 1 is configured |
| 12 | gm_dummy_en | 0x0 | R/W | Dummy waits for enabling, and the configuration is valid as 1 |
| 11 | gm_crb_en | 0x0 | R/W | Continuous read bit sending enable, configured as 1 |
| 10:7 | gm_data_md_sel | 0x0 | R/W | Mode selection of sending address: 4’b0000: single line mode 4’b0001: 4-line mode 4’b0100: single line merge mode 4’b0101: 4-line merge mode 4’b1000: DTR single line mode 4’b1001: DTR4 line mode 4’b1100: DTR single line merge mode 4’b1101: DTR4 line merge mode Others: Reverd |
| 6 | gm_addr_en | 0x0 | R/W | Enable the sending address. The configuration is 1 |
| 5:2 | gm_cmd_md_sel | 0x0 | R/W | Mode selection for sending command: 4’b0000: single line mode 4’b0001: 4-line mode 4’b0100: single line merge mode 4’b0101: 4-line merge mode 4’b1000: DTR single line mode 4’b1001: DTR4 line mode 4’b1100: DTR single line merge mode 4’b1101: DTR4 line merge mode Others: Reverd |
| 1 | gm_cmd_en | 0x0 | R/W | Send command enable, valid if 1 is configured |
| 0 | gm_en | 0x0 | R/W | The general mode is always enabled. If the configuration is 1, the bit bit will be cleared to 0 after it takes effect after writing 1 |
General Mode Configuration Register 1 (GM1_CFG)¶
Offset: 0x14
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:27 | Reserved | 0 | R/W | Reserved |
| 26 | gm_cmd_size | 0x0 | R/W | The data length of the command, which is the value of the bit+1 Byte |
| 25:24 | gm_addr_size | 0x0 | R/W | The data length of the address, which is the value of the bit+1 Byte |
| 23:16 | gm_crb_code | 0x0 | R/W | Continuous read bit data sent |
| 15:8 | gm_cmd_code1 | 0x0 | R/W | Command code data sent 1 |
| 7:0 | gm_cmd_code0 | 0x0 | R/W | Command code data sent 0 |
General Mode Read Write Address Configuration Register (GM_ADDR_CFG)¶
Offset: 0x18
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | gm_address | 0 | R/W | Read/write address in general mode |
General Mode Data Size Configuration Register (GM_DATA_SIZE_CFG)¶
Offset: 0x1C
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:20 | Reserved | 0 | R/W | Reserved |
| 19:0 | rw_data_size | 0 | R/W | Number of data bytes read and written, in Bytes |
Prefetch Read Mode Configuration Register (RD_CFG)¶
Offset: 0x20
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:23 | Reserved | 0 | R/W | Reserved |
| 22 | prefetch_en | 0 | R/W | The prefetch read mode is always enabled, and the configuration is 1 |
| 21:17 | rd_dummy_cycle | 0 | R/W | Cycle of Dummy waiting for flash |
| 16 | Reserved | 0 | R/W | Reserved |
| 15:12 | rd_data_md_sel | 0x0 | R/W | Data reading mode selection: 4’b0000: single line mode 4’b0001: 4-line mode 4’b0100: single line merge mode 4’b0101: 4-line merge mode 4’b1000: DTR single line mode 4’b1001: DTR4 line mode 4’b1100: DTR single line merge mode 4’b1101: DTR4 line merge mode Others: Reverd |
| 11 | rd_dummy_en | 0 | R/W | Dummy waits for enabling, and the configuration is valid as 1 |
| 10 | rd_crb_en | 0 | R/W | Continuous read bit sending enable, configured as 1 |
| 9:6 | rd_addr_md_sel | 0x0 | R/W | Mode selection of sending address: 4’b0000: single line mode 4’b0001: 4-line mode 4’b0100: single line merge mode 4’b0101: 4-line merge mode 4’b1000: DTR single line mode 4’b1001: DTR4 line mode 4’b1100: DTR single line merge mode 4’b1101: DTR4 line merge mode Others: Reverd |
| 5:2 | rd_cmd_md_sel | 0x0 | R/W | Mode selection for sending command: 4’b0000: single line mode 4’b0001: 4-line mode 4’b0100: single line merge mode 4’b0101: 4-line merge mode 4’b1000: DTR single line mode 4’b1001: DTR4 line mode 4’b1100: DTR single line merge mode 4’b1101: DTR4 line merge mode Others: Reverd |
| 1 | rd_cmd_en | 0 | R/W | Send command enable, valid if 1 is configured |
| 0 | rd_en | 0 | R/W | The prefetch read mode is always enabled, and the configuration is 1 |
Expected Read Mode Configuration Register 1 (RD1_CFG)¶
Offset: 0x24
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:27 | Reserved | 0 | R/W | Reserved |
| 26 | rd_cmd_size | 0x0 | R/W | The data length of the command, which is the value of the bit+1 Byte |
| 25:24 | rd_addr_size | 0x0 | R/W | The data length of the address, which is the value of the bit+1 Byte |
| 23:16 | rd_crb_code | 0x0 | R/W | Continuous read bit data sent |
| 15:8 | rd_cmd_code1 | 0x0 | R/W | Command code data sent 1 |
| 7:0 | rd_cmd_code0 | 0x0 | R/W | Command code data sent 0 |
FIFO Level Configuration Register (FIFO_LEVEL_CFG)¶
Offset: 0x30
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:19 | Reserved | 0 | R/W | Reserved |
| 18:13 | rfifo_amfull_level | 0x0 | R/W | Configure the threshold standard for the number of amfull (almost full) data in the read FIFO, and trigger the corresponding conditions when it is reached |
| 12:7 | rd_arfifo_amempty_levelddr_size | 0x0 | R/W | Configure the threshold standard for the number of amempty (almost empty) data in the read FIFO, and trigger the corresponding conditions when it is reached |
| 6:0 | wfifo_amfull_level | 0x0 | R/W | Configure the threshold standard for the number of amfull (almost full) data in the write FIFO, and trigger the corresponding conditions when it is reached |
Read/Write Cache Register 0 (RW_DATA0_CFG)¶
Offset: 0x34
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | rw_data_reg0 | 0 | R/W | Read/write cache, select the first WORD data when data is stored as a register |
Read/Write Cache Register 1 (RW_DATA1_CFG)¶
Offset: 0x38
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | rw_data_reg1 | 0 | R/W | Read/write cache, select the second WORD data when the data is stored as a register |
Interrupt Control Configuration Register (INT_CTRL_CFG)¶
Offset: 0x3C
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:6 | Reserved | 0 | R/W | Reserved |
| 5 | hready_error_int_en | 0 | R/W | thread Error interrupt enable, configured as 1 |
| 4 | ecc_error_int_en | 0 | R/W | ECC error interrupt enable, configured as 1 |
| 3 | gm_done_int_en | 0 | R/W | Interrupt enable is completed for general mode processing, and the configuration is valid as 1 |
| 2 | prefetch_md_close_int_en | 0 | R/W | The prefetch mode command completes the interrupt enable, and the configuration is valid as 1 |
| 1 | rfifo_under_flow_int_en | 0 | R/W | Interrupt enable when the read FIFO is lower than the preset value, and the configuration is 1 |
| 0 | wfifo_overflow_int_en | 0 | R/W | Interrupt enable when write FIFO is higher than the preset value, and the configuration is valid as 1 |
Status Register (STATE_REG)¶
Offset: 0x40
Reset value: 0x00000040
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:9 | Reserved | 0 | R/W | Reserved |
| 8 | main_ctrl_busy | 0 | R | Main control busy status, read-only, 1 is busy |
| 7 | arbt_busy | 0 | R | arbt busy status, read-only, 1 is busy |
| 6 | data_if_thread | 1 | R | The data is in the thread error state, read-only, and 1 is the state |
| 5 | hready_error_int | 0 | R/W | thread Error interrupt status. 1 is the trigger interrupt. This bit is written to 1 and cleared |
| 4 | ecc_error_int | 0 | R/W | ECC error interrupt status, 1 is trigger interrupt, and this bit is written to 1 to clear |
| 3 | gm_done_int | 0 | R/W | General mode processing completion interrupt status, 1 is trigger interrupt, this bit is written to 1 and cleared |
| 2 | prefetch_md_close_int | 0 | R/W | Prefetch mode command completion interrupt status, 1 is trigger interrupt, this bit is written to 1 and cleared |
| 1 | rfifo_under_flow_int | 0 | R/W | Interrupt status when the read FIFO is lower than the preset value, 1 is the trigger interrupt, and this bit is written to 1 to clear |
| 0 | wfifo_overflow_int | 0 | R/W | Write FIFO higher than the preset value interrupt status, 1 is the trigger interrupt, and this bit is written to 1 to clear |