System Control Unit SCU¶
The System Control Unit (SCU) is primarily responsible for managing the chip’s clock sources, generating and controlling certain clock signals, and handling interrupt control. Together with the DPMU module, it provides essential clock management and related core functions for the chip.
SCU Register Mapping¶
The base address of the system control unit register mapping is 0x40000000. See Table SCU-1 for details.
Table SCU-1 System Control Unit Register Mapping
| Offset | Name | Bit Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| 0x00 | SYS_CTRL_CFG | 32 | R/W | 0x00000401 | System control register |
| 0x0C | EXT_INT_CFG | 32 | R/W | 0x00,000,000 | External interrupt configuration register |
| 0x50 | SYSCFG_LOCK_CFG | 32 | R/W | 0x00000000 | System lock configuration register |
| 0x58 | CKCFG_LOCK_CFG | 32 | R/W | 0x00000000 | Clock configuration lock configuration register |
| 0x80 | CLKDIV_PARAM0_CFG | 32 | R/W | 0x1001808C | Frequency division parameter register 0 |
| 0x84 | CLKDIV_PARAM1_CFG | 32 | R/W | 0x00008208 | Frequency division parameter register 1 |
| 0x88 | CLKDIV_PARAM2_CFG | 32 | R/W | 0x03C0F03C | Frequency division parameter register 2 |
| 0xB0 | CLK_DIV_PARAM_EN_CFG | 32 | R/W | 0x00000000 | Frequency division parameter enable register |
| 0xC0 | SRC0_MCLK_CFG | 32 | R/W | 0x00000001 | MCLK source clock 0 configuration register |
| 0xC4 | SRC1_MCLK_CFG | 32 | R/W | 0x00000001 | MCLK source clock 1 configuration register |
| 0xC8 | SRC2_MCLK_CFG | 32 | R/W | 0x00,000,001 | MCLK source clock 2 configuration register |
| 0xD0 | MCLK0_CFG | 32 | R/W | 0x00000001 | IIS0 MCLK configuration register |
| 0xE0 | IIS0_CLK_SEL_CFG | 32 | R/W | 0x00000001 | IIS0 clock selection configuration register |
| 0xF0 | PAD_CLK_SEL_CFG | 32 | R/W | 0x00000009 | IIS pin clock selection configuration register |
| 0xF8 | PDM_CLK_SEL_CFG | 32 | R/W | 0x00000001 | PDM clock selection configuration register |
| 0x11C | SYS_CLKGATE_CFG0 | 32 | R/W | 0x00000FFC | System clock gating configuration register |
| 0x124 | AHB_CLKGATE_CFG | 32 | R/W | 0x0000007F | AHB bus module clock gating configuration register |
| 0x128 | APB0_CLKGATE_CFG | 32 | R/W | 0x00007FFF | APB0 bus module clock gating configuration register |
| 0x12C | APB1_CLKGATE_CFG | 32 | R/W | 0x000001FF | APB1 bus module clock gating configuration register |
| 0x178 | SCU_STATE_REG | 32 | R/W | 0x00000001 | SCU status register |
| 0x190 | AHB_RESET_CFG | 32 | R/W | 0x0000007E | AHB bus module software reset configuration register |
| 0x194 | APB0_RESET_CFG | 32 | R/W | 0x00000FFF | APB0 bus module software reset configuration register |
| 0x198 | APB1_RESET_CFG | 32 | R/W | 0x000001FF | APB1 bus module software reset configuration register |
| 0x1DC | WAKEUP_MASK_CFG | 32 | R/W | 0x00000000 | Wake up Mask configuration register |
| 0x1E4 | EXT0_FILTER_CFG | 32 | R/W | 0x0000FFFF | External interrupt 0 filter enable configuration register |
| 0x1E8 | EXT1_FILTER_CFG | 32 | R/W | 0x0000FFFF | External interrupt 1 filter enable configuration register |
| 0x1F4 | INT_STATE_REG | 32 | R/W | 0x00000000 | Interrupt status register |
System Control Register (SYS_CTRL_CFG)¶
Offset: 0x00
Reset value: 0x00000401
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:11 | Reserved | 0x0 | RW | Reserved |
| 10 | DTR_CLK_SEL | 0x1 | RW | DTR controller clock source: 0: clock before PLL frequency multiplication 1: PLL clock |
| 9 | RUN_IN_FLASH_EN | 0x1 | RW | Control system program running in FLASH (enable Flash XIP function): 1: running in FLASH 0: not running in FLASH |
| 8:5 | Reserved | 0x1 | RW | Reserved |
| 4:1 | NMI_INT_CTRL | 0x0 | RW | Configure the CPU fast interrupt as the following interrupt source: 0: Reserved 1: INT_IWDG 2：INT_WWDG 3：INT_EXT0 4：INT_EXT1 5：INT_TIMER0 6：INT_TIMER1 7：INT_UART0 8：INT_UART1 9：INT_UART2 10：INT_GPIO0 11：INT_GPIO1 12：INT_GPIO2 13：INT_VDT 14：Reserved 15：INT_ADC |
| 0 | SPI_BOOT | 0x1 | RW | The QSPI controller corresponding to the Flash has two modes: 0: The QSPI controller is in normal mode, not boot mode, used for reading and writing data in the Flash. 1: The QSPI controller is in boot mode, reading code from the Flash and executing it. After the chip is powered on, the system’s boot mode is controlled by the high or low voltage levels of specific pins at power-on. If the system is set to boot from the Flash, the SPI_BOOT bit must be set to 0 after the system has finished booting. This allows the QSPI controller to return to normal mode and read/write data in the Flash normally. |
External Interrupt Configuration Register (EXT_INT_CFG)¶
Offset: 0x0C
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:4 | Reserved | 0x0 | RW | Reserved |
| 3 | EXT1_INT_EN | 0x0 | RW | External Interrupt 1 Interrupt Enable: 1: A corresponding interrupt is generated when an external interrupt request occurs 0: The interrupt is not enabled |
| 2 | EXT0_INT_EN | 0x0 | RW | External Interrupt 0 Interrupt Enable: 1: A corresponding interrupt is generated when an external interrupt request occurs 0: Interrupt is not enabled |
| 1 | EXT1_INT_STATE | 0x0 | RW | External Interrupt 1 Status Bit: 1: External Interrupt Request Occurred 0: No External Interrupt Request Occurred Write 1 of this bit is cleared |
| 0 | EXT0_INT_STATE | 0x0 | RW | External Interrupt 0 Status Bit: 1: External Interrupt Request Occurred 0: No External Interrupt Request Occurred This bit is written to 1 and cleared |
System Lock Configuration Register (SYSCFG_LOCK_CFG)¶
Offset: 0x50
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | SYSCFG_LOCK | 0x0 | RW | When the software configures the system, it is necessary to write 0x51AC0FFE to this register to unlock it before writing the configuration of each register of the system control unit. Reading the value of this register has the following meanings: 1: this register is unlocked and can be written 0: this register is not unlocked and cannot be written |
Clock Configuration Lock Configuration Register (CKCFG_LOCK_CFG)¶
Offset: 0x58
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | CKCFG_LOCK | 0x0 | RW | When the software configures the PLL and clock gating related registers, you need to write 0x51AC0FFE to this register to unlock it, and then you can configure it and write any other value to lock it. Reading the value of this register has the following meanings: 1: this register is unlocked and can be written 0: this register is not unlocked and cannot be written. |
Frequency Division Parameter Register 0 (CLKDIV_PARAM0_CFG)¶
Offset: 0x80
Reset value: 0x1001808C
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31 | Reserved | 0x0 | RW | Reserved |
| 30:24 | TIMER_GPWM_DIV | 0x10 | RW | Clock division parameters of TIMER and PWM modules |
| 23:12 | ST_DIV | 0x18 | RW | Frequency division parameters of the CPU core tick clock |
| 11:9 | DTR_RAM_DIV | 0x0 | RW | Clock division parameters of RAM in DTR Flash module |
| 8:6 | DTR_DIV | 0x2 | RW | Clock division parameters of DTR Flash module |
| 5:0 | ADC_DIV | 0xC | RW | Clock division parameters of ADC module |
Frequency Division Parameter Register 1 (CLKDIV_PARAM1_CFG)¶
Offset: 0x84
Reset value: 0x00008208
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:18 | Reserved | 0x0 | RW | Reserved |
| 17:12 | UART2_DIV | 0x8 | RW | Clock division parameters of UART2 module |
| 11:6 | UART1_DIV | 0x8 | RW | Clock division parameters of UART1 module |
| 5:0 | UART0_DIV | 0x8 | RW | Clock division parameters of UART0 module |
Frequency Division Parameter Register 2 (CLKDIV_PARAM2_CFG)¶
Offset: 0x88
Reset value: 0x03C0F03C
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:30 | Reserved | 0x0 | RW | Reserved |
| 29:20 | SRC2_MCLK_DIV | 0x3C | RW | Frequency division parameter of MCLK source clock 2 |
| 19:10 | SRC1_MCLK_DIV | 0x3C | RW | Frequency division parameter of MCLK source clock 1 |
| 9:0 | SRC0_MCLK_DIV | 0x3C | RW | Frequency division parameter of MCLK source clock 0 |
Frequency Division Parameter Enable Register (CLK_DIV_PARAM_EN_CFG)¶
Offset: 0xB0
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:11 | Reserved | 0x0 | RW | Reserved |
| 10 | SRC2_MCLK_DIV_EN | 0x0 | RW | Frequency division parameter SRC2_MCLK_Update enable of DIV: 1: enable 0: disable |
| 9 | SRC1_MCLK_DIV_EN | 0x0 | RW | Frequency division parameter SRC1_MCLK_Update enable of DIV: 1: enable 0: disable |
| 8 | SRC0_MCLK_DIV_EN | 0x0 | RW | Frequency division parameter SRC0_MCLK_Update enable of DIV: 1: enable 0: disable |
| 7 | UART2_DIV_EN | 0x0 | RW | Frequency division parameter UART2_Update enable of DIV: 1: enable 0: disable |
| 6 | UART1_DIV_EN | 0x0 | RW | Frequency division parameter UART1_Update enable of DIV: 1: enable 0: disable |
| 5 | UART0_DIV_EN | 0x0 | RW | Frequency division parameter UART0_Update enable of DIV: 1: enable 0: disable |
| 4 | TIMER_GPWM_DIV_EN | 0x0 | RW | Frequency division parameter TIMER_GPWM_Update enable of DIV: 1: enable 0: disable |
| 3 | ST_DIV_EN | 0x0 | RW | Frequency division parameter ST_Update enable of DIV: 1: enable 0: disable |
| 2 | DTR_RAM_DIV_EN | 0x0 | RW | Frequency division parameter DTR_RAM_Update enable of DIV: 1: enable 0: disable |
| 1 | DTR_DIV_EN | 0x0 | RW | Frequency division parameter DTR_Update enable of DIV: 1: enable 0: disable |
| 0 | ADC_DIV_EN | 0x0 | RW | Frequency division parameter ADC_Update enable of DIV: 1: enable 0: disable |
MCLK Source Clock 0 Configuration Register (SRC0_MCLK_CFG)¶
Offset: 0xC0
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:3 | Reserved | 0x0 | RW | Reserved |
| 2:1 | SRC0_MCLK_SEL | 0x0 | RW | Clock of MCLK source 0: 0: system core clock 1: external crystal oscillator clock 2: internal RC crystal oscillator clock 3: clock input of chip MCLK pin |
| 0 | SRC0_MCLK_CKEN | 0x1 | RW | Clock gating of MCLK source 0: 0: close the clock 1: open the clock |
MCLK Source Clock 1 Configuration Register (SRC1_MCLK_CFG)¶
Offset: 0xC4
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:3 | Reserved | 0x0 | RW | Reserved |
| 2:1 | SRC1_MCLK_SEL | 0x0 | RW | Clock of source 1 of MCLK: 0: system core clock 1: external crystal oscillator clock 2: internal RC crystal oscillator clock 3: clock input of chip MCLK pin |
| 0 | SRC1_MCLK_CKEN | 0x1 | RW | Clock gating of source 1 of MCLK: 0: close the clock 1: open the clock |
MCLK Source Clock 2 Configuration Register (SRC2_MCLK_CFG)¶
Offset: 0xC8
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:3 | Reserved | 0x0 | RW | Reserved |
| 2:1 | SRC2_MCLK_SEL | 0x0 | RW | Clock of source 2 of MCLK: 0: system core clock 1: external crystal oscillator clock 2: internal RC crystal oscillator clock 3: clock input of chip MCLK pin |
| 0 | SRC2_MCLK_CKEN | 0x1 | RW | Clock gating of source 2 of MCLK: 0: close the clock 1: open the clock |
IIS0 MCLK Configuration Register (MCLK0_CFG)¶
Offset: 0xD0
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:6 | Reserved | 0x0 | RW | Reserved |
| 5:4 | MCLK0_FS_SEL | 0x0 | RW | Configure the oversampling rate of MCLK of IIS0: 0:128FS 1:192FS 2:256FS 3:384FS |
| 3 | MCLK0_WID_SEL | 0x0 | RW | Configure the frequency relationship ratio between SCK and LRCK: 1: SCK/LRCK=64 0: SCK/LRCK=32 |
| 2:1 | MCLK0_SEL | 0x0 | RW | Configure IIS0 MCLK Source: 0: MCLK0 1: MCLK1 2: MCLK2 3: Chip MCLK pin input clock |
| 0 | MCLK0_CKEN | 0x1 | RW | Clock gating of MCLK of IIS0: 0: Turn off the clock 1: Turn on the clock |
IIS0 Clock Selection Configuration Register (IIS0_CLK_SEL_CFG)¶
Offset: 0xE0
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:4 | Reserved | 0x0 | RW | Reserved |
| 3:1 | IIS0_CLK_SEL | 0x0 | RW | SCK/LRCK output source: 0: SCK/LRCK generated by MCLK0 1: SCK/LRCK generated by MCLK1 2: SCK/LRCK generated by MCLK2 3: external SCK/LRCK input by chip pin 4: ADC input clock of internal Codec 5: DAC input clock of internal Codec 6: input clock of PDM 7: input clock of PDM (the same function as 6) |
| 0 | IIS0_CLK_MUX_CKEN | 0x1 | RW | Clock gating after selecting the above clock source for the IIS0 module: 0: Turn off the clock 1: Turn on the clock |
IIS Pin Clock Selection Configuration Register (PAD_CLK_SEL_CFG)¶
Offset: 0xF0
Reset value: 0x00000009
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:9 | Reserved | 0x0 | RW | Reserved |
| 8 | PAD_SCK_LRCK_PAD_OEN | 0x0 | RW | Selection of chip pin direction of SCK and LRCK: 0: output 1: input |
| 7 | PAD_MCLK_PAD_OEN | 0x0 | RW | Selection of chip pin direction of MCLK: 0: output 1: input |
| 6:4 | PAD_IIS_CLK_SEL | 0x0 | RW | SCK/LRCK pin output source: 0: SCK/LRCK generated by MCLK0 1: SCK/LRCK generated by MCLK1 2: SCK/LRCK generated by MCLK2 3: Reserved 4: ADC input clock of internal Codec 5: DAC input clock of internal Codec 6: PDM input clock 7: PDM input clock (the same function as 6) |
| 3 | PAD_IIS_CLK_MUX_CKEN | 0x1 | RW | Clock gating after SCK and LRCK select the above clock source: 0: Turn off the clock 1: Turn on the clock |
| 2:1 | PAD_MCLK_SEL | 0x0 | RW | MCLK pin output source: 0: MCLK0 1: MCLK1 2: MCLK2 3: Low level |
| 0 | PAD_MCLK_MUX_CKEN | 0x1 | RW | MCLK Clock gating after selecting the above clock source: 0: Turn off the clock 1: Turn on the clock |
PDM Clock Selection Configuration Register (PDM_CLK_SEL_CFG)¶
Offset: 0xF8
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:3 | Reserved | 0x0 | RW | Reserved |
| 2:1 | PDM_MCLK_SEL | 0x0 | RW | MCLK source of PDM module: 0: MCLK0 1: MCLK1 2: MCLK2 3: clock input by MCLK hardware |
| 0 | PDM_MCLK_MUX_CKEN | 0x1 | RW | Clock gating after MCLK of PDM module selects the above clock source: 0: Turn off the clock 1: Turn on the clock |
System Clock Gating Configuration Register (SYS_CLKGATE_CFG0)¶
Offset: 0x11C
Reset value: 0x00000FFC
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:12 | Reserved | 0x0 | RW | Reserved |
| 11 | ROM_CKEN | 0x1 | RW | ROM module clock gating: 0: turn off the clock 1: turn on the clock |
| 10 | SRAM6_CLKEN | 0x1 | RW | Clock gating of SRAM6 module: 0: Turn off the clock 1: Turn on the clock |
| 9 | SRAM5_CLKEN | 0x1 | RW | Clock gating of SRAM5 module: 0: Turn off the clock 1: Turn on the clock |
| 8 | SRAM4_CLKEN | 0x1 | RW | Clock gating of SRAM4 module: 0: Turn off the clock 1: Turn on the clock |
| 7 | SRAM3_CLKEN | 0x1 | RW | Clock gating of SRAM3 module: 0: Turn off the clock 1: Turn on the clock |
| 6 | SRAM2_CLKEN | 0x1 | RW | Clock gating of SRAM2 module: 0: Turn off the clock 1: Turn on the clock |
| 5 | SRAM1_CLKEN | 0x1 | RW | Clock gating of SRAM1 module: 0: Turn off the clock 1: Turn on the clock |
| 4 | SRAM0_CLKEN | 0x1 | RW | SRAM0 module clock gating: 0: turn off the clock 1: turn on the clock |
| 3 | STCLK | 0x1 | RW | System tick clock STCLK module clock gating: 0: Turn off the clock 1: Turn on the clock |
| 2 | CPU_CORECLK | 0x1 | RW | Clock gating of CPU core clock module: 0: Turn off the clock 1: Turn on the clock |
| 1 | SLEEPDEEP | 0x0 | RW | Clock gating when the CPU is in deep sleep: 0: Turn off the clock 1: Turn on the clock |
| 0 | SLEEPING | 0x0 | RW | Clock gating during CPU sleep: 0: Turn off the clock 1: Turn on the clock |
Note 1: The above SRAM0 to SRAM6 together form 640KB SRAM in the chip. In normal use, please set all clocks to ON status
Note 2: The above deep sleep and sleep are two sleep modes of the CPU, which can be realized by directly writing the built-in registers of the CPU. When using this mode, you need to turn on the corresponding clock in advance. The user can refer to the relevant data of the CPU for setting
AHB Bus Module Clock Gating Configuration Register (AHB_CLKGATE_CFG)¶
Offset: 0x124
Reset value: 0x0000007F
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:5 | Reserved | 0x3 | RW | Reserved |
| 4 | DTR_CKEN | 0x1 | RW | Clock gating of DTR Flash module: 0: Turn off the clock 1: Turn on the clock |
| 3 | Reserved | 0x1 | RW | Reserved |
| 2 | ADC_CKEN | 0x1 | RW | Clock gating of ADC module: 0: Turn off the clock 1: Turn on the clock |
| 1 | GDMA_CKEN | 0x1 | RW | Clock gating of DMA module: 0: Turn off the clock 1: Turn on the clock |
| 0 | Reserved | 0x1 | RW | Reserved |
APB0 Bus Module Clock Gating Configuration Register (APB0_CLKGATE_CFG)¶
Offset: 0x128
Reset value: 0x00007FFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:14 | Reserved | 0x3 | RW | Reserved |
| 13 | WWDG_CPU_HALT_CKEN | 0x1 | RW | Window watchdog WWDG module clock gating when CPU is in HALT state: 0: turn off the clock 1: turn on the clock |
| 12 | CODEC_DA_CKEN | 0x1 | RW | Clock gating of CODEC module DAC: 0: Turn off the clock 1: Turn on the clock |
| 11 | CODEC_AD_CKEN | 0x1 | RW | Clock gating of CODEC module ADC: 0: Turn off the clock 1: Turn on the clock |
| 10 | TIMER3_CKEN | 0x1 | RW | TIMER3 module clock gating: 0: turn off the clock 1: turn on the clock |
| 9 | TIMER2_CKEN | 0x1 | RW | TIMER2 module clock gating: 0: turn off the clock 1: turn on the clock |
| 8 | TIMER1_CKEN | 0x1 | RW | TIMER1 module clock gating: 0: turn off the clock 1: turn on the clock |
| 7 | TIMER0_CKEN | 0x1 | RW | TIMER0 module clock gating: 0: turn off the clock 1: turn on the clock |
| 6 | GPWM3_CKEN | 0x1 | RW | Clock gating of PWM3 module: 0: Turn off the clock 1: Turn on the clock |
| 5 | GPWM2_CKEN | 0x1 | RW | Clock gating of PWM2 module: 0: Turn off the clock 1: Turn on the clock |
| 4 | GPWM1_CKEN | 0x1 | RW | Clock gating of PWM1 module: 0: Turn off the clock 1: Turn on the clock |
| 3 | GPWM0_CKEN | 0x1 | RW | Clock gating of PWM0 module: 0: Turn off the clock 1: Turn on the clock |
| 2 | PDM_CKEN | 0x1 | RW | Clock gating of PDM module: 0: Turn off the clock 1: Turn on the clock |
| 1 | IIC_CKEN | 0x1 | RW | Clock gating of IIC module: 0: Turn off the clock 1: Turn on the clock |
| 0 | WWDG_CKEN | 0x1 | RW | Clock gating of WWDG module: 0: Turn off the clock 1: Turn on the clock |
APB1 Bus Module Clock Gating Configuration Register (APB1_CLKGATE_CFG)¶
Offset: 0x12C
Reset value: 0x000001FF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:9 | Reserved | 0x3 | RW | Reserved |
| 8:6 | Reserved | 0x7 | RW | Reserved |
| 5 | IIS0_CKEN | 0x1 | RW | Clock gating of IIS0 module: 0: Turn off the clock 1: Turn on the clock |
| 4 | UART2_CKEN | 0x1 | RW | Clock gating of UART2 module: 0: Turn off the clock 1: Turn on the clock |
| 3 | UART1_CKEN | 0x1 | RW | Clock gating of UART1 module: 0: Turn off the clock 1: Turn on the clock |
| 2 | UART0_CKEN | 0x1 | RW | Clock gating of UART0 module: 0: Turn off the clock 1: Turn on the clock |
| 1 | GPIO1_CKEN | 0x1 | RW | Clock gating of GPIO1 module: 0: Turn off the clock 1: Turn on the clock |
| 0 | GPIO0_CKEN | 0x1 | RW | Clock gating of GPIO0 module: 0: Turn off the clock 1: Turn on the clock |
SCU Status Register (SCU_STATE_REG)¶
Offset: 0x178
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:5 | Reserved | 0x0 | RW | Reserved |
| 4 | CPU_DEEPSLEEP | 0x0 | RW | CPU deep sleep status query: 0: not in deep sleep status 1: in deep sleep status |
| 3 | CPU_SLEEP | 0x0 | RW | CPU sleep status query: 0: not in sleep status 1: in sleep status |
| 2 | PLL_LOCK_STATE | 0x0 | RW | PLL lock status query: 0: not locked 1: locked |
| 1 | BOOT_MODE | 0x0 | RW | System startup mode query: 0: on-chip ROM startup 1: on-chip SRAM startup |
| 0 | Reserved | 0x1 | RW | Reserved |
AHB Bus Module Software Reset Configuration Register (AHB_RESET_CFG)¶
Offset: 0x190
Reset value: 0x0000007E
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:5 | Reserved | 0x3 | RW | Reserved |
| 4 | DTR_RSTEN | 0x1 | RW | DTR Flash module software reset control: 0: reset 1: no reset |
| 3 | Reserved | 0x1 | RW | Reserved |
| 2 | ADC_RSTEN | 0x1 | RW | ADC module software reset control: 0: reset 1: no reset |
| 1 | GDMA_RSTEN | 0x1 | RW | DMA module software reset control: 0: reset 1: no reset |
| 0 | Reserved | 0x1 | RW | Reserved |
APB0 Bus Module Software Reset Configuration Register (APB0_RESET_CFG)¶
Offset: 0x194
Reset value: 0x00000FFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:12 | Reserved | 0x0 | RW | Reserved |
| 11 | TIMER23_RSTEN | 0x1 | RW | TIMER2 and TIMER3 module software reset control: 0: reset 1: no reset |
| 10 | Reserved | 0x1 | RW | Reserved |
| 9 | TIMER01_RSTEN | 0x1 | RW | TIMER0 and TIMER1 module software reset control: 0: reset 1: no reset |
| 8 | Reserved | 0x1 | RW | Reserved |
| 7 | GPWM23_RSTEN | 0x1 | RW | PWM2 and PWM3 module software reset control: 0: reset 1: no reset |
| 6 | Reserved | 0x1 | RW | Reserved |
| 5 | GPWM01_RSTEN | 0x1 | RW | PWM0 and PWM1 module software reset control: 0: reset 1: no reset |
| 4 | Reserved | 0x1 | RW | Reserved |
| 3 | CODEC_RSTEN | 0x1 | RW | CODEC module software reset control: 0: reset 1: no reset |
| 2 | PDM_RSTEN | 0x1 | RW | PDM module software reset control: 0: reset 1: no reset |
| 1 | IIC_RSTEN | 0x1 | RW | IIC module software reset control: 0: reset 1: no reset |
| 0 | WWDG_RSTEN | 0x1 | RW | Window watchdog WWDG module software reset control: 0: reset 1: no reset |
APB1 Bus Module Software Reset Configuration Register (APB1_RESET_CFG)¶
Offset: 0x198
Reset value: 0x000001FF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:6 | Reserved | 0x0 | RW | Reserved |
| 5 | IIS0_RSTEN | 0x1 | RW | IIS0 module software reset control: 0: reset 1: no reset |
| 4 | UART2_RSTEN | 0x1 | RW | UART2 module software reset control: 0: reset 1: no reset |
| 3 | UART1_RSTEN | 0x1 | RW | UART1 module software reset control: 0: reset 1: no reset |
| 2 | UART0_RSTEN | 0x1 | RW | UART0 module software reset control: 0: reset 1: no reset |
| 1 | GPIO1_RSTEN | 0x1 | RW | GPIO1 module software reset control: 0: reset 1: no reset |
| 0 | GPIO0_RSTEN | 0x1 | RW | GPIO0 module software reset control: 0: reset 1: no reset |
Wake Up Mask Configuration Register (WAKEUP_MASK_CFG)¶
Offset: 0x1DC
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:17 | Reserved | 0x0 | RW | Reserved |
| 16 | ADC_INT | 0x0 | RW | ADC module interrupt wake-up enable: 0: disable 1: enable |
| 15 | Reserved | 0x0 | RW | Reserved |
| 14 | VDT_INT | 0x0 | RW | VDT module interrupt wake-up enable: 0: disable 1: enable |
| 13 | IIS_INT | 0x0 | RW | IIS module interrupt wake-up enable: 0: disable 1: enable |
| 12 | GPIO2_INT | 0x0 | RW | GPIO2 module interrupt wake-up enable: 0: disable 1: enable |
| 11 | GPIO1_INT | 0x0 | RW | GPIO1 module interrupt wake-up enable: 0: disable 1: enable |
| 10 | GPIO0_INT | 0x0 | RW | GPIO0 module interrupt wake-up enable: 0: disable 1: enable |
| 9 | UART2_INT | 0x0 | RW | UART2 module interrupt wake-up enable: 0: disable 1: enable |
| 8 | UART1_INT | 0x0 | RW | UART1 module interrupt wake-up enable: 0: disable 1: enable |
| 7 | UART0_INT | 0x0 | RW | UART0 module interrupt wake-up enable: 0: disable 1: enable |
| 6 | TIMER1_INT | 0x0 | RW | TIMER1 module interrupt wake-up enable: 0: disable 1: enable |
| 5 | TIMER0_INT | 0x0 | RW | TIMER0 module interrupt wake-up enable: 0: disable 1: enable |
| 4 | WWDG_INT | 0x0 | RW | Window watchdog WWDG module interrupt wake-up enable: 0: disable 1: enable |
| 3 | IWDG_INT | 0x0 | RW | Independent watchdog IWDG module interrupt wake-up enable: 0: disable 1: enable |
| 2 | EXT_INT1 | 0x0 | RW | External interrupt 1 module interrupt wake-up enable: 0: disable 1: enable |
| 1 | EXT_INT0 | 0x0 | RW | External interrupt 0 Module interrupt wake-up enable: 0: Disable 1: Enable |
| 0 | SCU_INT | 0x0 | RW | SCU module interrupt wake-up enable: 0: disable 1: enable |
External Interrupt 0 Filter Enable Configuration Register (EXT0_FILTER_CFG)¶
Offset: 0x1E4
Reset value: 0x0000FFFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:21 | Reserved | 0x0 | RW | Reserved |
| 20 | FILTER0_EN | 0x0 | RW | External interrupt 0 Input signal filtering function enable: 0: disable 1: enable |
| 19:0 | EXT0_FILTER | 0xFFFF | RW | External interrupt 0 filtering parameter |
External Interrupt 1 Filter Enable Configuration Register (EXT1_FILTER_CFG)¶
Offset: 0x1E8
Reset value: 0x0000FFFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:21 | Reserved | 0x0 | RW | Reserved |
| 20 | FILTER1_EN | 0x0 | RW | External interrupt 1 Input signal filtering function enable: 0: disable 1: enable |
| 19:0 | EXT1_FILTER | 0xFFFF | RW | External interrupt 1 filter parameter |
Note: External interrupt 0 and external interrupt 1 can be digitally filtered. During filtering, count with one crystal oscillator clock cycle, and the cumulative count value is greater than or equal to EXT0_FILTER/EXT1_The value of FILTER will trigger the corresponding external interrupt. EXT0_FILTER/EXT1_The larger the FILTER value is, the longer the external interrupt is required to maintain the effective trigger level
Interrupt Status Register (INT_STATE_REG)¶
Offset: 0x1F4
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:17 | Reserved | 0x0 | W1C | Reserved |
| 16 | ADC_INT_WAKE | 0x0 | W1C | ADC module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 15 | Reserved | 0x0 | W1C | Reserved |
| 14 | VDT_INT_WAKE | 0x0 | W1C | VDT module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 13 | IIS_INT_WAKE | 0x0 | W1C | IIS module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 12 | GPIO2_INT_WAKE | 0x0 | W1C | GPIO2 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 11 | GPIO1_INT_WAKE | 0x0 | W1C | GPIO1 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 10 | GPIO0_INT_WAKE | 0x0 | W1C | GPIO0 Module Interruption Wakeup Status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 9 | UART2_INT_WAKE | 0x0 | W1C | UART2 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 8 | UART1_INT_WAKE | 0x0 | W1C | UART1 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 7 | UART0_INT_WAKE | 0x0 | W1C | UART0 module interrupt Wake up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 6 | TIMER1_INT_WAKE | 0x0 | W1C | TIMER1 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 5 | TIMER0_INT_WAKE | 0x0 | W1C | TIMER0 Module Interruption Wakeup Status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 4 | WWDG_INT_WAKE | 0x0 | W1C | Window watchdog WWDG module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 3 | IWDG_INT_WAKE | 0x0 | W1C | Independent watchdog IWDG module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 2 | EXT_INT1_WAKE | 0x0 | W1C | External Interrupt 1 Module Interrupt Wakeup Status: 0: Interrupt does not cause system wake-up 1: Interrupt causes system wake-up, write 1 to this bit to clear the status |
| 1 | EXT_INT0_WAKE | 0x0 | W1C | External interrupt 0 Module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 0 | SCU_INT_WAKE | 0x0 | W1C | SCU module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |