System Control Unit SCU¶
The system control unit is mainly responsible for the clock source of the chip, the generation and control of some clock signals, interrupt control and other functions. This module and the DPMU module together provide the basic functions of the chip such as clock control.
SCU register mapping¶
The base address of the system control unit register mapping is 0x40000000. See Table SCU-1 for details.
Table SCU-1 System Control Unit Register Mapping
| Offset | Name | Bit Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| 0x00 | SYS_ CTRL_ CFG | 32 | R/W | 0x00000401 | System control register |
| 0x0C | EXT_ INT_ CFG | 32 | R/W | 0x00,000,000 | External interrupt configuration register |
| 0x50 | SYSCFG_ LOCK_ CFG | 32 | R/W | 0x00000000 | System lock configuration register |
| 0x58 | CKCFG_ LOCK_ CFG | 32 | R/W | 0x00000000 | Clock configuration lock configuration register |
| 0x80 | CLKDIV_ PARAM0_ CFG | 32 | R/W | 0x1001808C | Frequency division parameter register 0 |
| 0x84 | CLKDIV_ PARAM1_ CFG | 32 | R/W | 0x00008208 | Frequency division parameter register 1 |
| 0x88 | CLKDIV_ PARAM2_ CFG | 32 | R/W | 0x03C0F03C | Frequency division parameter register 2 |
| 0xB0 | CLK_ DIV_ PARAM_ EN_ CFG | 32 | R/W | 0x00000000 | Frequency division parameter enable register |
| 0xC0 | SRC0_ MCLK_ CFG | 32 | R/W | 0x00000001 | MCLK source clock 0 configuration register |
| 0xC4 | SRC1_ MCLK_ CFG | 32 | R/W | 0x00000001 | MCLK source clock 1 configuration register |
| 0xC8 | SRC2_ MCLK_ CFG | 32 | R/W | 0x00,000,001 | MCLK source clock 2 configuration register |
| 0xD0 | MCLK0_ CFG | 32 | R/W | 0x00000001 | IIS0 MCLK configuration register |
| 0xE0 | IIS0_ CLK_ SEL_ CFG | 32 | R/W | 0x00000001 | IIS0 clock selection configuration register |
| 0xF0 | PAD_ CLK_ SEL_ CFG | 32 | R/W | 0x00000009 | IIS pin clock selection configuration register |
| 0xF8 | PDM_ CLK_ SEL_ CFG | 32 | R/W | 0x00000001 | PDM clock selection configuration register |
| 0x11C | SYS_ CLKGATE_ CFG0 | 32 | R/W | 0x00000FFC | System clock gating configuration register |
| 0x124 | AHB_ CLKGATE_ CFG | 32 | R/W | 0x0000007F | AHB bus module clock gating configuration register |
| 0x128 | APB0_ CLKGATE_ CFG | 32 | R/W | 0x00007FFF | APB0 bus module clock gating configuration register |
| 0x12C | APB1_ CLKGATE_ CFG | 32 | R/W | 0x000001FF | APB1 bus module clock gating configuration register |
| 0x178 | SCU_ STATE_ REG | 32 | R/W | 0x00000001 | SCU status register |
| 0x190 | AHB_ RESET_ CFG | 32 | R/W | 0x0000007E | AHB bus module software reset configuration register |
| 0x194 | APB0_ RESET_ CFG | 32 | R/W | 0x00000FFF | APB0 bus module software reset configuration register |
| 0x198 | APB1_ RESET_ CFG | 32 | R/W | 0x000001FF | APB1 bus module software reset configuration register |
| 0x1DC | WAKEUP_ MASK_ CFG | 32 | R/W | 0x00000000 | Wake up Mask configuration register |
| 0x1E4 | EXT0_ FILTER_ CFG | 32 | R/W | 0x0000FFFF | External interrupt 0 filter enable configuration register |
| 0x1E8 | EXT1_ FILTER_ CFG | 32 | R/W | 0x0000FFFF | External interrupt 1 filter enable configuration register |
| 0x1F4 | INT_ STATE_ REG | 32 | R/W | 0x00000000 | Interrupt status register |
System control register (SYS_CTRL_CFG)¶
Offset: 0x00
Reset value: 0x00000401
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:11 | Reserved | 0x0 | RW | Reserved |
| 10 | DTR_ CLK_ SEL | 0x1 | RW | DTR controller clock source: 0: clock before PLL frequency multiplication 1: PLL clock |
| 9 | RUN_ IN_ FLASH_ EN | 0x1 | RW | Control system program running in FLASH (enable Flash XIP function): 1: running in FLASH 0: not running in FLASH |
| 8:5 | Reserved | 0x1 | RW | Reserved |
| 4:1 | NMI_ INT_ CTRL | 0x0 | RW | Configure the CPU fast interrupt as the following interrupt source: 0: Reserved 1: INT_ IWDG 2：INT_ WWDG 3：INT_ EXT0 4：INT_ EXT1 5：INT_ TIMER0 6：INT_ TIMER1 7：INT_ UART0 8：INT_ UART1 9：INT_ UART2 10：INT_ GPIO0 11：INT_ GPIO1 12：INT_ GPIO2 13：INT_ VDT 14：Reserved 15：INT_ ADC |
| 0 | SPI_ BOOT | 0x1 | RW | Enable the BOOT mode of the QSPI controller corresponding to Flash:, After the system is started, the SPI_ If the BOOT bit is set to 0, the QSPI controller corresponding to Flash can restore to the normal mode, and the data in Flash can be read and written normally |
External interrupt configuration register (EXT_INT_CFG)¶
Offset: 0x0C
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:4 | Reserved | 0x0 | RW | Reserved |
| 3 | EXT1_ INT_ EN | 0x0 | RW | External Interrupt 1 Interrupt Enable: 1: A corresponding interrupt is generated when an external interrupt request occurs 0: The interrupt is not enabled |
| 2 | EXT0_ INT_ EN | 0x0 | RW | External Interrupt 0 Interrupt Enable: 1: A corresponding interrupt is generated when an external interrupt request occurs 0: Interrupt is not enabled |
| 1 | EXT1_ INT_ STATE | 0x0 | RW | External Interrupt 1 Status Bit: 1: External Interrupt Request Occurred 0: No External Interrupt Request Occurred Write 1 of this bit is cleared |
| 0 | EXT0_ INT_ STATE | 0x0 | RW | External Interrupt 0 Status Bit: 1: External Interrupt Request Occurred 0: No External Interrupt Request Occurred This bit is written to 1 and cleared |
System lock configuration register (SYSCFG_LOCK_CFG)¶
Offset: 0x50
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | SYSCFG_ LOCK | 0x0 | RW | When the software configures the system, it is necessary to write 0x51AC0FFE to this register to unlock it before writing the configuration of each register of the system control unit. Reading the value of this register has the following meanings: 1: this register is unlocked and can be written 0: this register is not unlocked and cannot be written |
Clock configuration lock configuration register (CKCFG_LOCK_CFG)¶
Offset: 0x58
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | CKCFG_ LOCK | 0x0 | RW | When the software configures the PLL and clock gating related registers, you need to write 0x51AC0FFE to this register to unlock it, and then you can configure it and write any other value to lock it. Reading the value of this register has the following meanings: 1: this register is unlocked and can be written 0: this register is not unlocked and cannot be written. |
Frequency division parameter register 0 (CLKDIV_PARAM0_CFG)¶
Offset: 0x80
Reset value: 0x1001808C
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31 | Reserved | 0x0 | RW | Reserved |
| 30:24 | TIMER_ GPWM_ DIV | 0x10 | RW | Clock division parameters of TIMER and PWM modules |
| 23:12 | ST_ DIV | 0x18 | RW | Frequency division parameters of the CPU core tick clock |
| 11:9 | DTR_ RAM_ DIV | 0x0 | RW | Clock division parameters of RAM in DTR Flash module |
| 8:6 | DTR_ DIV | 0x2 | RW | Clock division parameters of DTR Flash module |
| 5:0 | ADC_ DIV | 0xC | RW | Clock division parameters of ADC module |
Frequency division parameter register 1 (CLKDIV_PARAM1_CFG)¶
Offset: 0x84
Reset value: 0x00008208
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:18 | Reserved | 0x0 | RW | Reserved |
| 17:12 | UART2_ DIV | 0x8 | RW | Clock division parameters of UART2 module |
| 11:6 | UART1_ DIV | 0x8 | RW | Clock division parameters of UART1 module |
| 5:0 | UART0_ DIV | 0x8 | RW | Clock division parameters of UART0 module |
Frequency division parameter register 2 (CLKDIV_PARAM2_CFG)¶
Offset: 0x88
Reset value: 0x03C0F03C
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:30 | Reserved | 0x0 | RW | Reserved |
| 29:20 | SRC2_ MCLK_ DIV | 0x3C | RW | Frequency division parameter of MCLK source clock 2 |
| 19:10 | SRC1_ MCLK_ DIV | 0x3C | RW | Frequency division parameter of MCLK source clock 1 |
| 9:0 | SRC0_ MCLK_ DIV | 0x3C | RW | Frequency division parameter of MCLK source clock 0 |
Frequency division parameter enable register (CLK_DIV_PARAM_EN_CFG)¶
Offset: 0xB0
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:11 | Reserved | 0x0 | RW | Reserved |
| 10 | SRC2_ MCLK_ DIV_ EN | 0x0 | RW | Frequency division parameter SRC2_ MCLK_ Update enable of DIV: 1: enable 0: disable |
| 9 | SRC1_ MCLK_ DIV_ EN | 0x0 | RW | Frequency division parameter SRC1_ MCLK_ Update enable of DIV: 1: enable 0: disable |
| 8 | SRC0_ MCLK_ DIV_ EN | 0x0 | RW | Frequency division parameter SRC0_ MCLK_ Update enable of DIV: 1: enable 0: disable |
| 7 | UART2_ DIV_ EN | 0x0 | RW | Frequency division parameter UART2_ Update enable of DIV: 1: enable 0: disable |
| 6 | UART1_ DIV_ EN | 0x0 | RW | Frequency division parameter UART1_ Update enable of DIV: 1: enable 0: disable |
| 5 | UART0_ DIV_ EN | 0x0 | RW | Frequency division parameter UART0_ Update enable of DIV: 1: enable 0: disable |
| 4 | TIMER_ GPWM_ DIV_ EN | 0x0 | RW | Frequency division parameter TIMER_ GPWM_ Update enable of DIV: 1: enable 0: disable |
| 3 | ST_ DIV_ EN | 0x0 | RW | Frequency division parameter ST_ Update enable of DIV: 1: enable 0: disable |
| 2 | DTR_ RAM_ DIV_ EN | 0x0 | RW | Frequency division parameter DTR_ RAM_ Update enable of DIV: 1: enable 0: disable |
| 1 | DTR_ DIV_ EN | 0x0 | RW | Frequency division parameter DTR_ Update enable of DIV: 1: enable 0: disable |
| 0 | ADC_ DIV_ EN | 0x0 | RW | Frequency division parameter ADC_ Update enable of DIV: 1: enable 0: disable |
MCLK source clock 0 configuration register (SRC0_MCLK_CFG)¶
Offset: 0xC0
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:3 | Reserved | 0x0 | RW | Reserved |
| 2:1 | SRC0_ MCLK_ SEL | 0x0 | RW | Clock of MCLK source 0: 0: system core clock 1: external crystal oscillator clock 2: internal RC crystal oscillator clock 3: clock input of chip MCLK pin |
| 0 | SRC0_ MCLK_ CKEN | 0x1 | RW | Clock gating of MCLK source 0: 0: close the clock 1: open the clock |
MCLK source clock 1 configuration register (SRC1_MCLK_CFG)¶
Offset: 0xC4
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:3 | Reserved | 0x0 | RW | Reserved |
| 2:1 | SRC1_ MCLK_ SEL | 0x0 | RW | Clock of source 1 of MCLK: 0: system core clock 1: external crystal oscillator clock 2: internal RC crystal oscillator clock 3: clock input of chip MCLK pin |
| 0 | SRC1_ MCLK_ CKEN | 0x1 | RW | Clock gating of source 1 of MCLK: 0: close the clock 1: open the clock |
MCLK source clock 2 configuration register (SRC2_MCLK_CFG)¶
Offset: 0xC8
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:3 | Reserved | 0x0 | RW | Reserved |
| 2:1 | SRC2_ MCLK_ SEL | 0x0 | RW | Clock of source 2 of MCLK: 0: system core clock 1: external crystal oscillator clock 2: internal RC crystal oscillator clock 3: clock input of chip MCLK pin |
| 0 | SRC2_ MCLK_ CKEN | 0x1 | RW | Clock gating of source 2 of MCLK: 0: close the clock 1: open the clock |
IIS0 MCLK configuration register (MCLK0_CFG)¶
Offset: 0xD0
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:6 | Reserved | 0x0 | RW | Reserved |
| 5:4 | MCLK0_ FS_ SEL | 0x0 | RW | Configure the oversampling rate of MCLK of IIS0: 0:128FS 1:192FS 2:256FS 3:384FS |
| 3 | MCLK0_ WID_ SEL | 0x0 | RW | Configure the frequency relationship ratio between SCK and LRCK: 1: SCK/LRCK=64 0: SCK/LRCK=32 |
| 2:1 | MCLK0_ SEL | 0x0 | RW | Configure IIS0 MCLK Source: 0: MCLK0 1: MCLK1 2: MCLK2 3: Chip MCLK pin input clock |
| 0 | MCLK0_ CKEN | 0x1 | RW | Clock gating of MCLK of IIS0: 0: Turn off the clock 1: Turn on the clock |
IIS0 clock selection configuration register (IIS0_CLK_SEL_CFG)¶
Offset: 0xE0
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:4 | Reserved | 0x0 | RW | Reserved |
| 3:1 | IIS0_ CLK_ SEL | 0x0 | RW | SCK/LRCK output source: 0: SCK/LRCK generated by MCLK0 1: SCK/LRCK generated by MCLK1 2: SCK/LRCK generated by MCLK2 3: external SCK/LRCK input by chip pin 4: ADC input clock of internal Codec 5: DAC input clock of internal Codec 6: input clock of PDM 7: input clock of PDM (the same function as 6) |
| 0 | IIS0_ CLK_ MUX_ CKEN | 0x1 | RW | Clock gating after selecting the above clock source for the IIS0 module: 0: Turn off the clock 1: Turn on the clock |
IIS pin clock selection configuration register (PAD_CLK_SEL_CFG)¶
Offset: 0xF0
Reset value: 0x00000009
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:9 | Reserved | 0x0 | RW | Reserved |
| 8 | PAD_ SCK_ LRCK_ PAD_ OEN | 0x0 | RW | Selection of chip pin direction of SCK and LRCK: 0: output 1: input |
| 7 | PAD_ MCLK_ PAD_ OEN | 0x0 | RW | Selection of chip pin direction of MCLK: 0: output 1: input |
| 6:4 | PAD_ IIS_ CLK_ SEL | 0x0 | RW | SCK/LRCK pin output source: 0: SCK/LRCK generated by MCLK0 1: SCK/LRCK generated by MCLK1 2: SCK/LRCK generated by MCLK2 3: Reserved 4: ADC input clock of internal Codec 5: DAC input clock of internal Codec 6: PDM input clock 7: PDM input clock (the same function as 6) |
| 3 | PAD_ IIS_ CLK_ MUX_ CKEN | 0x1 | RW | Clock gating after SCK and LRCK select the above clock source: 0: Turn off the clock 1: Turn on the clock |
| 2:1 | PAD_ MCLK_ SEL | 0x0 | RW | MCLK pin output source: 0: MCLK0 1: MCLK1 2: MCLK2 3: Low level |
| 0 | PAD_ MCLK_ MUX_ CKEN | 0x1 | RW | MCLK Clock gating after selecting the above clock source: 0: Turn off the clock 1: Turn on the clock |
PDM clock selection configuration register (PDM_CLK_SEL_CFG)¶
Offset: 0xF8
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:3 | Reserved | 0x0 | RW | Reserved |
| 2:1 | PDM_ MCLK_ SEL | 0x0 | RW | MCLK source of PDM module: 0: MCLK0 1: MCLK1 2: MCLK2 3: clock input by MCLK hardware |
| 0 | PDM_ MCLK_ MUX_ CKEN | 0x1 | RW | Clock gating after MCLK of PDM module selects the above clock source: 0: Turn off the clock 1: Turn on the clock |
System clock gating configuration register (SYS_CLKGATE_CFG0)¶
Offset: 0x11C
Reset value: 0x00000FFC
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:12 | Reserved | 0x0 | RW | Reserved |
| 11 | ROM_ CKEN | 0x1 | RW | ROM module clock gating: 0: turn off the clock 1: turn on the clock |
| 10 | SRAM6_ CLKEN | 0x1 | RW | Clock gating of SRAM6 module: 0: Turn off the clock 1: Turn on the clock |
| 9 | SRAM5_ CLKEN | 0x1 | RW | Clock gating of SRAM5 module: 0: Turn off the clock 1: Turn on the clock |
| 8 | SRAM4_ CLKEN | 0x1 | RW | Clock gating of SRAM4 module: 0: Turn off the clock 1: Turn on the clock |
| 7 | SRAM3_ CLKEN | 0x1 | RW | Clock gating of SRAM3 module: 0: Turn off the clock 1: Turn on the clock |
| 6 | SRAM2_ CLKEN | 0x1 | RW | Clock gating of SRAM2 module: 0: Turn off the clock 1: Turn on the clock |
| 5 | SRAM1_ CLKEN | 0x1 | RW | Clock gating of SRAM1 module: 0: Turn off the clock 1: Turn on the clock |
| 4 | SRAM0_ CLKEN | 0x1 | RW | SRAM0 module clock gating: 0: turn off the clock 1: turn on the clock |
| 3 | STCLK | 0x1 | RW | System tick clock STCLK module clock gating: 0: Turn off the clock 1: Turn on the clock |
| 2 | CPU_ CORECLK | 0x1 | RW | Clock gating of CPU core clock module: 0: Turn off the clock 1: Turn on the clock |
| 1 | SLEEPDEEP | 0x0 | RW | Clock gating when the CPU is in deep sleep: 0: Turn off the clock 1: Turn on the clock |
| 0 | SLEEPING | 0x0 | RW | Clock gating during CPU sleep: 0: Turn off the clock 1: Turn on the clock |
Note 1: The above SRAM0 to SRAM6 together form 640KB SRAM in the chip. In normal use, please set all clocks to ON status Note 2: The above deep sleep and sleep are two sleep modes of the CPU, which can be realized by directly writing the built-in registers of the CPU. When using this mode, you need to turn on the corresponding clock in advance. The user can refer to the relevant data of the CPU for setting
AHB bus module clock gating configuration register (AHB_CLKGATE_CFG)¶
Offset: 0x124
Reset value: 0x0000007F
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:5 | Reserved | 0x3 | RW | Reserved |
| 4 | DTR_ CKEN | 0x1 | RW | Clock gating of DTR Flash module: 0: Turn off the clock 1: Turn on the clock |
| 3 | Reserved | 0x1 | RW | Reserved |
| 2 | ADC_ CKEN | 0x1 | RW | Clock gating of ADC module: 0: Turn off the clock 1: Turn on the clock |
| 1 | GDMA_ CKEN | 0x1 | RW | Clock gating of DMA module: 0: Turn off the clock 1: Turn on the clock |
| 0 | Reserved | 0x1 | RW | Reserved |
APB0 bus module clock gating configuration register (APB0_CLKGATE_CFG)¶
Offset: 0x128
Reset value: 0x00007FFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:14 | Reserved | 0x3 | RW | Reserved |
| 13 | WWDG_ CPU_ HALT_ CKEN | 0x1 | RW | Window watchdog WWDG module clock gating when CPU is in HALT state: 0: turn off the clock 1: turn on the clock |
| 12 | CODEC_ DA_ CKEN | 0x1 | RW | Clock gating of CODEC module DAC: 0: Turn off the clock 1: Turn on the clock |
| 11 | CODEC_ AD_ CKEN | 0x1 | RW | Clock gating of CODEC module ADC: 0: Turn off the clock 1: Turn on the clock |
| 10 | TIMER3_ CKEN | 0x1 | RW | TIMER3 module clock gating: 0: turn off the clock 1: turn on the clock |
| 9 | TIMER2_ CKEN | 0x1 | RW | TIMER2 module clock gating: 0: turn off the clock 1: turn on the clock |
| 8 | TIMER1_ CKEN | 0x1 | RW | TIMER1 module clock gating: 0: turn off the clock 1: turn on the clock |
| 7 | TIMER0_ CKEN | 0x1 | RW | TIMER0 module clock gating: 0: turn off the clock 1: turn on the clock |
| 6 | GPWM3_ CKEN | 0x1 | RW | Clock gating of PWM3 module: 0: Turn off the clock 1: Turn on the clock |
| 5 | GPWM2_ CKEN | 0x1 | RW | Clock gating of PWM2 module: 0: Turn off the clock 1: Turn on the clock |
| 4 | GPWM1_ CKEN | 0x1 | RW | Clock gating of PWM1 module: 0: Turn off the clock 1: Turn on the clock |
| 3 | GPWM0_ CKEN | 0x1 | RW | Clock gating of PWM0 module: 0: Turn off the clock 1: Turn on the clock |
| 2 | PDM_ CKEN | 0x1 | RW | Clock gating of PDM module: 0: Turn off the clock 1: Turn on the clock |
| 1 | IIC_ CKEN | 0x1 | RW | Clock gating of IIC module: 0: Turn off the clock 1: Turn on the clock |
| 0 | WWDG_ CKEN | 0x1 | RW | Clock gating of WWDG module: 0: Turn off the clock 1: Turn on the clock |
APB1 bus module clock gating configuration register (APB1_CLKGATE_CFG)¶
Offset: 0x12C
Reset value: 0x000001FF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:9 | Reserved | 0x3 | RW | Reserved |
| 8:6 | Reserved | 0x7 | RW | Reserved |
| 5 | IIS0_ CKEN | 0x1 | RW | Clock gating of IIS0 module: 0: Turn off the clock 1: Turn on the clock |
| 4 | UART2_ CKEN | 0x1 | RW | Clock gating of UART2 module: 0: Turn off the clock 1: Turn on the clock |
| 3 | UART1_ CKEN | 0x1 | RW | Clock gating of UART1 module: 0: Turn off the clock 1: Turn on the clock |
| 2 | UART0_ CKEN | 0x1 | RW | Clock gating of UART0 module: 0: Turn off the clock 1: Turn on the clock |
| 1 | GPIO1_ CKEN | 0x1 | RW | Clock gating of GPIO1 module: 0: Turn off the clock 1: Turn on the clock |
| 0 | GPIO0_ CKEN | 0x1 | RW | Clock gating of GPIO0 module: 0: Turn off the clock 1: Turn on the clock |
SCU Status Register (SCU_STATE_REG)¶
Offset: 0x178
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:5 | Reserved | 0x0 | RW | Reserved |
| 4 | CPU_ DEEPSLEEP | 0x0 | RW | CPU deep sleep status query: 0: not in deep sleep status 1: in deep sleep status |
| 3 | CPU_ SLEEP | 0x0 | RW | CPU sleep status query: 0: not in sleep status 1: in sleep status |
| 2 | PLL_ LOCK_ STATE | 0x0 | RW | PLL lock status query: 0: not locked 1: locked |
| 1 | BOOT_ MODE | 0x0 | RW | System startup mode query: 0: on-chip ROM startup 1: on-chip SRAM startup |
| 0 | Reserved | 0x1 | RW | Reserved |
AHB Bus Module Software Reset Configuration Register (AHB_RESET_CFG)¶
Offset: 0x190
Reset value: 0x0000007E
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:5 | Reserved | 0x3 | RW | Reserved |
| 4 | DTR_ RSTEN | 0x1 | RW | DTR Flash module software reset control: 0: reset 1: no reset |
| 3 | Reserved | 0x1 | RW | Reserved |
| 2 | ADC_ RSTEN | 0x1 | RW | ADC module software reset control: 0: reset 1: no reset |
| 1 | GDMA_ RSTEN | 0x1 | RW | DMA module software reset control: 0: reset 1: no reset |
| 0 | Reserved | 0x1 | RW | Reserved |
APB0 bus module software reset configuration register (APB0_RESET_CFG)¶
Offset: 0x194
Reset value: 0x00000FFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:12 | Reserved | 0x0 | RW | Reserved |
| 11 | TIMER23_ RSTEN | 0x1 | RW | TIMER2 and TIMER3 module software reset control: 0: reset 1: no reset |
| 10 | Reserved | 0x1 | RW | Reserved |
| 9 | TIMER01_ RSTEN | 0x1 | RW | TIMER0 and TIMER1 module software reset control: 0: reset 1: no reset |
| 8 | Reserved | 0x1 | RW | Reserved |
| 7 | GPWM23_ RSTEN | 0x1 | RW | PWM2 and PWM3 module software reset control: 0: reset 1: no reset |
| 6 | Reserved | 0x1 | RW | Reserved |
| 5 | GPWM01_ RSTEN | 0x1 | RW | PWM0 and PWM1 module software reset control: 0: reset 1: no reset |
| 4 | Reserved | 0x1 | RW | Reserved |
| 3 | CODEC_ RSTEN | 0x1 | RW | CODEC module software reset control: 0: reset 1: no reset |
| 2 | PDM_ RSTEN | 0x1 | RW | PDM module software reset control: 0: reset 1: no reset |
| 1 | IIC_ RSTEN | 0x1 | RW | IIC module software reset control: 0: reset 1: no reset |
| 0 | WWDG_ RSTEN | 0x1 | RW | Window watchdog WWDG module software reset control: 0: reset 1: no reset |
APB1 bus module software reset configuration register (APB1_RESET_CFG)¶
Offset: 0x198
Reset value: 0x000001FF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:6 | Reserved | 0x0 | RW | Reserved |
| 5 | IIS0_ RSTEN | 0x1 | RW | IIS0 module software reset control: 0: reset 1: no reset |
| 4 | UART2_ RSTEN | 0x1 | RW | UART2 module software reset control: 0: reset 1: no reset |
| 3 | UART1_ RSTEN | 0x1 | RW | UART1 module software reset control: 0: reset 1: no reset |
| 2 | UART0_ RSTEN | 0x1 | RW | UART0 module software reset control: 0: reset 1: no reset |
| 1 | GPIO1_ RSTEN | 0x1 | RW | GPIO1 module software reset control: 0: reset 1: no reset |
| 0 | GPIO0_ RSTEN | 0x1 | RW | GPIO0 module software reset control: 0: reset 1: no reset |
Wake up Mask configuration register (WAKEUP_MASK_CFG)¶
Offset: 0x1DC
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:17 | Reserved | 0x0 | RW | Reserved |
| 16 | ADC_ INT | 0x0 | RW | ADC module interrupt wake-up enable: 0: disable 1: enable |
| 15 | Reserved | 0x0 | RW | Reserved |
| 14 | VDT_ INT | 0x0 | RW | VDT module interrupt wake-up enable: 0: disable 1: enable |
| 13 | IIS_ INT | 0x0 | RW | IIS module interrupt wake-up enable: 0: disable 1: enable |
| 12 | GPIO2_ INT | 0x0 | RW | GPIO2 module interrupt wake-up enable: 0: disable 1: enable |
| 11 | GPIO1_ INT | 0x0 | RW | GPIO1 module interrupt wake-up enable: 0: disable 1: enable |
| 10 | GPIO0_ INT | 0x0 | RW | GPIO0 module interrupt wake-up enable: 0: disable 1: enable |
| 9 | UART2_ INT | 0x0 | RW | UART2 module interrupt wake-up enable: 0: disable 1: enable |
| 8 | UART1_ INT | 0x0 | RW | UART1 module interrupt wake-up enable: 0: disable 1: enable |
| 7 | UART0_ INT | 0x0 | RW | UART0 module interrupt wake-up enable: 0: disable 1: enable |
| 6 | TIMER1_ INT | 0x0 | RW | TIMER1 module interrupt wake-up enable: 0: disable 1: enable |
| 5 | TIMER0_ INT | 0x0 | RW | TIMER0 module interrupt wake-up enable: 0: disable 1: enable |
| 4 | WWDG_ INT | 0x0 | RW | Window watchdog WWDG module interrupt wake-up enable: 0: disable 1: enable |
| 3 | IWDG_ INT | 0x0 | RW | Independent watchdog IWDG module interrupt wake-up enable: 0: disable 1: enable |
| 2 | EXT_ INT1 | 0x0 | RW | External interrupt 1 module interrupt wake-up enable: 0: disable 1: enable |
| 1 | EXT_ INT0 | 0x0 | RW | External interrupt 0 Module interrupt wake-up enable: 0: Disable 1: Enable |
| 0 | SCU_ INT | 0x0 | RW | SCU module interrupt wake-up enable: 0: disable 1: enable |
External interrupt 0 filter enable configuration register (EXT0_FILTER_CFG)¶
Offset: 0x1E4
Reset value: 0x0000FFFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:21 | Reserved | 0x0 | RW | Reserved |
| 20 | FILTER0_ EN | 0x0 | RW | External interrupt 0 Input signal filtering function enable: 0: disable 1: enable |
| 19:0 | EXT0_ FILTER | 0xFFFF | RW | External interrupt 0 filtering parameter |
External interrupt 1 filter enable configuration register (EXT1_FILTER_CFG)¶
Offset: 0x1E8
Reset value: 0x0000FFFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:21 | Reserved | 0x0 | RW | Reserved |
| 20 | FILTER1_ EN | 0x0 | RW | External interrupt 1 Input signal filtering function enable: 0: disable 1: enable |
| 19:0 | EXT1_ FILTER | 0xFFFF | RW | External interrupt 1 filter parameter |
Note: External interrupt 0 and external interrupt 1 can be digitally filtered. During filtering, count with one crystal oscillator clock cycle, and the cumulative count value is greater than or equal to EXT0_ FILTER/EXT1_ The value of FILTER will trigger the corresponding external interrupt. EXT0_ FILTER/EXT1_ The larger the FILTER value is, the longer the external interrupt is required to maintain the effective trigger level
Interrupt status register (INT_STATE_REG)¶
Offset: 0x1F4
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:17 | Reserved | 0x0 | W1C | Reserved |
| 16 | ADC_ INT_ WAKE | 0x0 | W1C | ADC module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 15 | Reserved | 0x0 | W1C | Reserved |
| 14 | VDT_ INT_ WAKE | 0x0 | W1C | VDT module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 13 | IIS_ INT_ WAKE | 0x0 | W1C | IIS module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 12 | GPIO2_ INT_ WAKE | 0x0 | W1C | GPIO2 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 11 | GPIO1_ INT_ WAKE | 0x0 | W1C | GPIO1 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 10 | GPIO0_ INT_ WAKE | 0x0 | W1C | GPIO0 Module Interruption Wakeup Status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 9 | UART2_ INT_ WAKE | 0x0 | W1C | UART2 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 8 | UART1_ INT_ WAKE | 0x0 | W1C | UART1 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 7 | UART0_ INT_ WAKE | 0x0 | W1C | UART0 module interrupt Wake up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 6 | TIMER1_ INT_ WAKE | 0x0 | W1C | TIMER1 module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 5 | TIMER0_ INT_ WAKE | 0x0 | W1C | TIMER0 Module Interruption Wakeup Status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 4 | WWDG_ INT_ WAKE | 0x0 | W1C | Window watchdog WWDG module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 3 | IWDG_ INT_ WAKE | 0x0 | W1C | Independent watchdog IWDG module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 2 | EXT_ INT1_ WAKE | 0x0 | W1C | External Interrupt 1 Module Interrupt Wakeup Status: 0: Interrupt does not cause system wake-up 1: Interrupt causes system wake-up, write 1 to this bit to clear the status |
| 1 | EXT_ INT0_ WAKE | 0x0 | W1C | External interrupt 0 Module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |
| 0 | SCU_ INT_ WAKE | 0x0 | W1C | SCU module interrupt wake-up status: 0: Interruption does not cause system wake-up 1: Interruption causes system wake-up, write 1 to this bit to clear the status |