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DMA

DMA realizes a working mode that transfers data between peripherals and/or memory without CPU participation and completely relies on hardware, thus greatly liberating CPU and improving efficiency. Through DMA, the system can quickly transfer data between peripherals and memory, memory and memory, without any interference of CPU.

Function introduction

The main features of DMA controller are as follows:

  • 1 DMA channel, 4 DMA requests, each channel only supports one-way transmission
  • Support single request and burst request
  • Support memory memory, memory peripheral, peripheral memory transfer
  • Support DMA transmission of decentralized/continuous addresses by using linked lists
  • Hardware DMA channel priority, channel 0 has the highest priority, and channel 2 has the lowest priority
  • Two AHB bus masters
  • Support DMA source address and destination address increment or non increment
  • DMA burst size is configurable
  • There is a 4-word FIFO inside each channel
  • Support 8-bit, 16 bit and 32-bit transmission
  • DMA transmission is completed or DMA transmission error generates interrupt request
  • DMA interrupt request can be masked
  • Interrupt request status before DMA masking can be queried

In order for DMA to work normally, the following configuration sequence shall be met during software configuration:

  1. Configure DMACxSrcAddr, DMACxDestAddr, DMACxLLI, DMACxControl, DMACxConfiguration and other channel registers
  2. Enable DMA channel
  3. Enable DMA controller

The chip’s DMA supports two channels. The source and destination of the channel can be configured according to the transmission direction. The software determines which DMA channel to use when requesting data transmission according to the DMA controller.

The DMA request is a burst request, and the related register is DMACBREQ [15:0]. DMA requests can be generated by software (DMACSoftBReq, DMACSoftSReq) and hardware. Allocation of hardware DMA requests is shown in Table D-1.

Table D-1 DMA burst transmission request allocation

Offset Name Description
0 DTR Flash DTR Flash Channel
1-3 Reserved Reserved
4 UART0_ RX UART0 Receive
5 UART0_ TX UART0 send
6 UART1_ RX UART1 reception
7 UART1_ TX UART1 sending
8 Reserved Reserved
9 Reserved Reserved
10-15 Reserved Reserved

The above DMA supported modules have independent access addresses. The DTR Flash module is 0x6,000,000, UART0 is 0x61,000,000, and UART1 is 0x62,000,000.

Register Mapping

The register mapping base address of DMA controller DMAC is 0x40001000. See Table D-2 for details.

Table D-2 DMA Register Mapping

Offset Name Bit Width Type Reset Value Description
0x000 DMACIntStatus 8 RO 0x00 Interrupt status register
0x004 DMACIntTCStatus 8 RO 0x00 Transfer count interrupt status register
0x008 DMACIntTCClear 8 WO 0x00 Transfer count interrupt clear register
0x00C DMACIntErrorStatus 8 RO 0x00 Transmission error interrupt status register
0x010 DMACIntErrClr 8 WO 0x00 Transfer error interrupt clear register
0x014 DMACRawIntTCStatus 8 RO 0x00 Transfer count raw interrupt status register
0x018 DMACRawIntErrorStatus 8 RO 0x00 Transfer error original interrupt status register
0x01C DMACEnbldChns 8 RO 0x00 Channel enable status register
0x030 DMACConfiguration 3 R/W 0x0 Configuration register
0x100 DMACxSrcAddr 32 R/W 0x00000000 Channel source address register
0x104 DMACxDestAddr 32 R/W 0x00000000 Channel destination address register
0x108 DMACxLLI 32 R/W 0x00000000 Channel linked list register
0x10C DMACxControl 32 R/W 0x00000000 Channel control register
0x110 DMACxConfiguration 20 R/W 0x00000 Channel configuration register

Interrupt Status Register (DMACIntStatus)

Offset: 0x000

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:8 Reserved 0 R Reserved
7:0 IntStatus 0x00 R Status of DMA interrupt after masking. The lower three bits are valid, and 1 indicates an interrupt

Transfer Count Interrupt Status Register (DMACIntTCStatus)

Offset: 0x004

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:8 Reserved 0 R Reserved
7: 0 IntTCStatus 0x00 R Interrupt terminal count request status, the lower three bits are valid, and 1 indicates transmission count interrupt

Transfer count interrupt clear register (DMACIntTCClear)

Offset: 0x008

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:8 Reserved 0 W Reserved
7: 0 IntTCClear 0x00 W The terminal count request is cleared. The lower 3 bits are valid. Write 1 clears the transmission count interrupt status

Transfer error interrupt status register (DMACIntErrorStatus)

Offset: 0x00C

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:8 Reserved 0 R Reserved
7: 0 IntErrorStatus 0x00 R Interrupt error status, the lower 3 bits are valid, and 1 indicates transmission error interrupt

Transfer error interrupt clear register (DMACIntErrClr)

Offset: 0x010

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:8 Reserved 0 W Reserved
7:0 IntErrClr 0x00 W Interrupt error clearing, the lower 3 bits are valid, and writing 1 means clearing transmission error interrupt

Transfer Count Raw Interrupt Status Register (DMACRawIntTCStatus)

Offset: 0x014

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:8 Reserved 0 R Reserved
7: 0 RawIntTCStatus 0x00 R Status of terminal count interrupt before shielding. The lower 3 bits are valid, and 1 indicates that a transmission count original interrupt has occurred

Transfer error raw interrupt status register (DMACRawIntErrorStatus)

Offset: 0x018

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:8 Reserved 0 R Reserved
7: 0 RawIntErrorStatus 0x00 R Status of error interrupt before masking. The lower three bits are valid, and 1 indicates that a transmission error occurred and the original interrupt occurred

Channel Enable Status Register (DMACEnbldChns)

Offset: 0x01C

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:8 Reserved 0 R Reserved
7: 0 EnabledChannels 0x00 R Channel enable status, the lower three bits are valid, and 1 means the corresponding channel is enabled

Configuration register (DMACConfiguration)

Offset: 0x030

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:1 Reserved 0 R/W Reserved
0 E 0 R/W DMAC enable:
0: Not enable
1: Enable
This bit is reset to 0. Disable DMAC to reduce power consumption.

Channel source address register (DMACxSrcAddr)

Offset: 0x100

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:0 SrcAddr 0 R/W DMA source address

Channel destination address register (DMACxDestAddr)

Offset: 0x104

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:0 DestAddr 0 R/W DMA destination address

Channel linked list register (DMACxLLI)

Offset: 0x108

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:2 LLI 0x00000000 R/W Link list item. Bit [31:2] of the next LLI address, and address bit [1:0] is 0.
1 Reserved 0 R/W Reserved
0 LM 0 R/W AHB primary selection is used to load the next LLI
0: AHB primary 1
1: AHB primary 2

Channel control register (DMACxControl)

Offset: 0x10C

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31 I 0 R/W Terminal count interrupt enable bit. It controls whether the current LLI will trigger the terminal count interrupt.
30:28 Prot 0x0 R/W Protection
27 DI 0 R/W Terminal count interrupt enable bit. It controls whether the current LLI expects to trigger a terminal count interrupt. Destination Increment: The destination address is incremented after each transmission.
26 SI 0 R/W Source increment. After setting, the source address is incremented after each transmission.
25 D 0 R/W Destination AHB host selection:
0: Select AHB host 1 for destination transmission
1: Select AHB host 2 for destination transmission
24 S 0 R/W Source AHB host selection:
0: Source transmission selects AHB host 1
1: Source transmission selects AHB host 2
23:21 DWidth 0x0 R/W Target transmission width. It is illegal for the transmission width to exceed the AHB main bus width. The source and target widths can be different from each other. The hardware will automatically package and unpack data when needed.
20: 18 SWidth 0x0 R/W Source transmission width. It is illegal for the transmission width to exceed the AHB main bus width. The source and target widths can be different from each other. The hardware will automatically package and unpack data when needed.
17: 15 DBSize 0x0 R/W Source transmission size. It is illegal for the transmission size to exceed the AHB master bus size. The source and target sizes can be different from each other. The hardware will automatically package and unpack data when needed.
14: 12 SBSize 0x0 R/W Source burst size. Indicates the number of transmissions that make up the source burst. This value must be set to the burst size of the source peripheral, or the memory boundary size if the source is memory.
11: 0 TransferSize 0x000 R/W Transfer size. When DMAC is a flow controller, write this field to set the transmission size
The data read from this field represents the number of transfers completed on the target bus. Reading registers when a channel is active does not provide useful information because the channel may have processed the read value when the software processes it. You should only use a channel when it is enabled and then disabled.

Channel configuration register (DMACxConfiguration)

Offset: 0x110

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:19 EN 0x0000 R/W POR power down control bit
0: ON
1: OFF, POR_ RESET=POR_ VDD
18 H 0 R/W Pause:
0: Enable DMA request
1: Ignore additional source DMA requests
The contents of the channel FIFO are discharged. You can use this value with the active bit and the channel enable bit to disable DMA channels completely.
17 A 0 R Active:
0: No data in the FIFO channel
1: Data in the channel’s FIFO
You can use this value together with the pause bit and the channel enable bit to completely disable the DMA channel.
16 L 0 R/W Lock: When set to 1, this bit enables locked transmission.
15 ITC 0 R/W Terminal count interrupt mask. When cleared, this bit interrupts the terminal count of the relevant channel.
14 IE 0 R/W Interrupt error mask. When cleared, this bit masks the error interrupt of the relevant channel.
13: 11 FlowCntrl 0x0 R/W Flow control and transmission type. This value indicates the flow controller and transmission type. The flow controller can be a DMAC, a source peripheral, or a target peripheral. The transmission type may be memory to memory, memory to peripheral device, peripheral device to memory, or peripheral device to peripheral device.
10 Reserved 0 R/W Reserved
9: 6 DestPeripheral 0x0 R/W Target peripheral device. This value selects the DMA target request peripheral. If the destination of the transfer is memory, this field is ignored.
5 Reserved 0 R/W Reserved
4: 1 SrcPeripheral 0x0 R/W Target peripheral device. This value selects the DMA target request peripheral. If the destination of the transfer is memory, this field is ignored.
0 E 0 R/W Channel enable bit. Reading this bit indicates whether the channel is currently enabled or disabled:
0: the channel is not enabled
1: the channel is enabled