IIS¶
Function introduction¶
Multi channel IIS is built in the chip, and IIS0 is available externally. This interface can be used to interface with external 16/24/32 bit stereo digital audio signal encoding and decoding circuits, and can be used in situations where CODEC inside the chip cannot meet the application requirements.
The receiver has the following characteristics:
- Support AHB bus for data transmission and APB bus for register configuration;
- Support abnormal detection of LRCK, SCK and DMA request signal after receiving data, and generate interrupt signal, which can be cleared by writing 1 in software;
- Support continuous and discontinuous transmission;
- The software can be configured to send and receive data in the following formats: IIS, left aligned and right aligned;
- The software can be configured with the bit width of receiving and transmitting data: 16bit, 20bit, 24bit, 32bit;
- LRCK and SCK proportional software can be matched: 1:32, 1:64;
- Audio channel data can be combined and configured (single and dual channel independent configuration): when receiving, two 16bit data are combined into 32bit, when sending, two 16bit data are compressed into a 32bit data for transmission, and the combination enable can be configured through software;
- The software can be configured to exchange left and right audio channel data when receiving or sending;
- The software can be configured to send FIFO to trigger the empty threshold: half empty and quarter empty;
- The software can be configured to receive FIFO full trigger threshold: ¼ full, ⅛ full, 1/16 full and 1/32 full;
- Enable the transceiver channel switch through software configuration;
- The receiving and transmitting data channel supports the mute function (left and right channels can be muted independently during data transmission), mono and dual channel stereo functions;
- The depth of the transmit FIFO is 32, the width is 32, and the depth of the receive FIFO is 128, the width is 32;
- Support DMA data transmission;
- Support FIFO overflow interrupt;
- The receiving and sending channels are completely independent, using a set of IIS SCK and LRCK clocks respectively.
There is a dedicated DMA channel for IIS transmission, which will not be described in detail here. Complete function examples and driver codes have been included in the chip supporting SDK development kit, and users can call them directly.
Register Mapping¶
The base address of IIS0 register mapping is 0x40025000. See Table IIS-1 for detailed register mapping.
Table IIS-1 IIS0 Register Mapping
| Offset | Name | Bit Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| 0x00 | IISINT | 32 | R/W | 0x00000000 | IIS interrupt query register |
| 0x10 | IISTX0CTRL | 32 | R/W | 0x00000000 | IIS0 send control register |
| 0x20 | IISRX0CTRL | 32 | R/W | 0x00000000 | IIS0 receive control register |
| 0x30 | IISLOADCTRL | 32 | R/W | 0x00000000 | IIS load enable control register |
| 0x34 | IISCHKEN_DMA_RX0 | 32 | R/W | 0x00000000 | IIS0 receive DMA request detection register |
| 0x40 | IISCHKEN_RX0 | 32 | R/W | 0x00,000,000 | IIS0 receive clock detection register |
| 0x50 | IISCHKEN_TX0 | 32 | R/W | 0x00000000 | IIS0 sending clock detection register |
IIS Interrupt Query Register (IISINT)¶
Offset: 0x00
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:27 | Reserved | 0x0000 | R/W | Reserved |
| 26 | tt0_err_int | 0 | R/W | Transmit channel 0 data enable signal generates too fast interrupt flag bit, write 1 to clear |
| 25:24 | Reserved | 0 | R/W | Reserved |
| 23 | tt0_err_int | 0 | R/W | Receive channel 0 data enable signal generates too fast interrupt flag bit, write 1 to clear |
| 22:9 | Reserved | 0 | R/W | Reserved |
| 8 | rx0_fifo_down_int | 0 | R/W | rx0_Overflow interrupt flag bit under fifo, write 1 to clear |
| 7 | rx0_fifo_over_int | 0 | R/W | rx0_Overflow interrupt flag bit on fifo, write 1 to clear |
| 6 | tx0_fifo_down_int | 0 | R/W | tx0_Overflow interrupt flag bit under fifo, write 1 to clear |
| 5 | tx0_fifo_over_int | 0 | R/W | tx0_Overflow interrupt flag bit on fifo, write 1 to clear |
| 4 | lrck_tx0_int | 0 | R/W | Send channel 0 LRCK clock CHK interrupt flag bit, write 1 clear |
| 3 | sck_tx0_int | 0 | R/W | Send channel 0 LRCK clock CHK interrupt flag bit, write 1 clear |
| 2 | dma_rx0_int | 0 | R/W | dma_rx0_interrupt flag bit detected by req, write 1 to clear |
| 1 | lrck_rx0_int | 0 | R/W | Receive channel 0 LRCK clock CHK interrupt flag bit, write 1 clear |
| 0 | sck_rx0_int | 0 | R/W | Receive channel 0 SCK clock CHK interrupt flag bit, write 1 clear |
IIS0 Send Control Register (IISTX0CTRL)¶
Offset: 0x10
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:17 | Reserved | 0 | R/W | Reserved |
| 16 | tx_swap | 0 | R/W | When transmitting, the left and right audio channels are exchanged (the left audio channel transmitting in mono channel changes to the right audio channel). Setting it to 1 is valid |
| 15 | tx_merge | 0 | R/W | Dual channel merge together (can be configured only when tx_mono is 0, and must be 16bit). Setting it to 1 is valid |
| 14 | tx_merge_mono | 0 | R/W | mono merge together (can be configured only when tx_mono is 1, and must be 16bit). Setting it to 1 is valid |
| 13 | tx_mono | 0 | R/W | Selection of mono and dual channels: 1: mono 0: dual channels |
| 12:11 | tx_df | 0 | R/W | Data transmission format: 0: IIS 1: Left alignment 2: Right alignment |
| 10 | tx_sck_lrck | 0 | R/W | Proportional relationship between SCK and LRCK on IIS bus (both master and slave are valid): 1: SCK=64 * LRCK 0: SCK=32 * LRCK (only 16bit can be configured) |
| 9 | txch_copy | 0 | R/W | Sending channel copy function. Single channel data can be copied to dual channels for sending (only when tx_mono is 1, it can be configured). It is valid when set to 1 |
| 8 | txch_r_Mute | 0 | R/W | Mute the right audio channel data, set to 1 |
| 7 | txch_l_Mute | 0 | R/W | Send left audio channel data mute, set to 1 |
| 6:4 | txch_Dw | 0 | R/W | Sending data width: 0:16bit 1:24bit 2:32bit 3:20bit |
| 3 | txfifo_Trig | 0 | R/W | Send FIFO trigger level configuration: 0: Half empty 1:¼ empty |
| 2: 1 | Reserved | 0 | R/W | Reserved |
| 0 | tx_en | 0 | R/W | Enable the sending channel, and set it to 1 |
IIS0 Receive Control Register (IISRX0CTRL)¶
Offset: 0x20
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31 | Reserved | 0 | R/W | Reserved |
| 30 | rx_ch_merge | 0 | R/W | Whether to participate in the merge (not only one ch_merge can be configured to be valid). Set it to 1 to be valid |
| 29:28 | rx_df | 0 | R/W | Data transmission format: 0: IIS 1: Left alignment 2: Right alignment |
| 27 | rx_sck_lrck | 0 | R/W | Proportional relationship between SCK and LRCK on IIS bus (both master and slave are valid): 1: SCK=64 * LRCK 0: SCK=32 * LRCK (only 16bit can be configured) |
| 26 | rx_mute | 0 | R/W | Receive channel mute enable: 1: mute, receive 0 0: normal mode |
| 25 | rx_merge_mono | 0 | R/W | The data of two 16bit mono channels are merged together (rx_mono must be 1 to be configured, and must be 16bit). Setting it to 1 is valid |
| 24 | rx_merge | 0 | R/W | Two 16bit data of dual channels are merged together (rx_mono must be 0 to be configured, and must be 16bit), and 1 is valid |
| 23:18 | Reserved | 0 | R/W | Reserved |
| 17 | rx_swap | 0 | R/W | Data exchange enable, set to 1 |
| 16 | rx_mono | 0 | R/W | Receiver channel setting: 0: Stereo 1: mono |
| 15: 9 | Reserved | 0 | R/W | Reserved |
| 8:6 | rxch_dw | 0 | R/W | Received data width: 0:16bit 1:24bit 2:32bit 3:20bit |
| 5:4 | rxfifo_trig | 0 | R/W | Receive FIFO trigger level configuration: 0:¼ full 1:⅛ full 2:1/16 full 3:1/32 full |
| 3: 1 | Reserved | 0 | R/W | Reserved |
| 0 | rx_en | 0 | R/W | Receive channel enable, set to 1 |
IIS Load Enable Control Register (IISLOADCTRL)¶
Offset: 0x30
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:11 | Reserved | 0 | R/W | Reserved |
| 10 | tx_load_en | 0 | R/W | Data transmission channel configuration information loading enable signal, which is set to 1 valid (read all the registers to 0 before configuring); Even if the transmission channel is configured to be on or off, this bit will not take effect if it is not configured |
| 9: 1 | Reserved | 0 | R/W | Reserved |
| 0 | rx_load_en | 0 | R/W | Data receiving channel configuration information loading enable signal, which is set to 1 valid (read all the registers to 0 before configuring); Even if the receiving channel is configured to be on or off, this bit will not take effect if it is not configured |
IIS0 Receive DMA Request Detection Register (IISCHKEN_DMA_RX0)¶
Offset: 0x34
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:17 | Reserved | 0 | R/W | Reserved |
| 16 | chk_dma_en | 0 | R/W | RX1_DMA_REQ request detection enable, set to 1 |
| 15:0 | chk_dma_num | 0 | R/W | Threshold of DMA count value |
IIS0 Receive Clock Detection Register (IISCHKN_RX0)¶
Offset: 0x40
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:21 | Reserved | 0 | R/W | Reserved |
| 20:1 | chk_rx_num | 0 | R/W | Threshold value of the IIS receive clock (shared by LRCK and SCK) detection count |
| 0 | chk_rx_en | 0 | R/W | IIS receive clock (shared by LRCK and SCK) detection enable, set to 1 and valid |
IIS0 Send Clock Detection Register (IISCHKEN_TX0)¶
Offset: 0x50
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:21 | Reserved | 0 | R/W | Reserved |
| 20:1 | chk_tx_num | 0 | R/W | Threshold value of IIS sending clock (shared by LRCK and SCK) detection count |
| 0 | chk_tx_en | 0 | R/W | IIS sending clock (shared by LRCK and SCK) detection enable, set to 1 and valid |