Independent watchdog (IWDG)

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Introduction

IWDG (Independent Watchdog) watchdog timer is a hardware timing circuit, which is mainly used to detect whether the system fails. The independent watchdog module is based on a 32bit down counter and uses a clock independent of the PLCK to count. When the count value reaches 0, an interrupt request counter overload initial value is generated to count down again. When the count value reaches 0 again, if the interrupt is not cleared, a reset request is generated and the counter stops counting.

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API

Function name	Description
iwdg_ Init	Initialize the IWDG device
iwdg_ Open	Start the IWDG device
iwdg_ Close	Stop the IWDG device
iwdg_ feed	IWDG device feeding dog

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Example

The following code configures and starts IWDG to feed dogs for 1s:

scu_ set_ device_ gate(HAL_IWDG_BASE, ENABLE);
eclic_ irq_ enable(IWDG_IRQn);
/*Open the reset configuration of IWDG*/
dpmu_ iwdg_ reset_ system_ config();
/*Configure IWDG and start*/
iwdg_ init_ t init;
init. irq = iwdg_ irqen_ enable;
init. res = iwdg_ resen_ enable;
init. count = get_ ipcore_ clk() / 16;      // IWDG clock is obtained from IPCORE through 16 frequency division
iwdg_ init(IWDG,init);
iwdg_ open(IWDG);