Window Watchdog (WWTD)¶
Function introduction¶
The clock of the window watchdog is obtained from the APB clock PCLK frequency division. After use, if the software fails to “feed the dog” in time before the counter reaches the specified value, reset or interrupt will occur. In addition, the WWTD also has a configurable window value. If the software “feeds the dog” before or after the count value reaches the lower limit value of the window, it will also cause an interrupt or reset. Therefore, the software must “feed the dog” within a limited time window.
The main features of the window watchdog are:
- Clock from PCLK frequency division
- Support window based services
- Support normal mode and pre warning alarm mode
- Under normal mode, reset request can be generated immediately if dog feeding timing is wrong, counter is out of range, and dog feeding value is written incorrectly
- In the Pre warning alarm mode, the first time the upper bound is crossed, an interrupt is generated, and the second time the upper bound is crossed, a reset request is generated; The dog feeding value is wrong or the timing of dog feeding is before the lower bound, and a reset request is generated
- Lock register to avoid misoperation of register
Register Mapping¶
The base address of WWTD register mapping is 0x40010000, and the specific register mapping is shown in Table W-1.
| Offset | Name | Bit Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| 0x00 | WDT_ CTR | 32 | R/W | 0x00000000 | Control register |
| 0x04 | WDT_ SCALE | 32 | R/W | 0x00000001 | Frequency division register |
| 0x08 | WDT_ SRV | 32 | WO | - | Dog feeding value register |
| 0x0C | WDT_ WLB | 32 | R/W | 0x00000000 | Window lower bound register |
| 0x10 | WDT_ WUB | 32 | R/W | 0xFFFFFFFF | Window upper bound register |
| 0x14 | WDT_ LOCK | 32 | R/W | 0x00000000 | Unlock command register |
| 0x18 | WDT_ COUNT | 32 | RO | 0x00000000 | Count value register |
| 0x1C | WDT_ STATUS | 32 | RO | 0x00000000 | Status register |
Control register (WDT_CTR)¶
Offset: 0x00
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:7 | Reserved | 0x00000000 | R/W | Reserved |
| 6 | INT_ EN | 0 | R/W | Interrupt generation enable: 0: Disable 1: Enable |
| 5 | RST_ EN | 0 | R/W | Reset generation enable: 0: Disable 1: Enable |
| 4 | WIND_ EN | 0 | R/W | Window function switch: 0: feed the dog within the upper limit 1: feed the dog within the window |
| 3 | HALT_ EN | 0 | R/W | Reserved |
| 2 | MODE | 0 | R/W | Working mode: 0: Normal mode 1: pre warning alarm mode |
| 1 | CLK_ SEL | 0 | R/W | Clock selection: 0: clock after PCLK frequency division 1: external input clock |
| 0 | GLB_ ENB | 0 | R/W | WWTD enable: 0: disable 1: enable |
Frequency division register (WDT_SCALE)¶
Offset: 0x04
Reset value: 0x00000001
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:16 | Reserved | 0x0000 | R/W | Reserved |
| 15:0 | WDT_ SCALE | 0x0001 | R/W | Frequency division register. When the clock after PCLK frequency division is selected as the timing reference clock, this register is used as the frequency division coefficient of PCLK. No frequency division when configured as 0 or 1 |
Dog feeding value register (WDT_SRV)¶
Offset: 0x08
Reset value:-
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | WDT_ SRV | - | WO | Dog feeding value register: Writing 0xABADC0DE to this register in the window means dog feeding. Writing other values will generate a reset request. If the interrupt request has been generated, writing 0xABADC0DE will clear the interrupt request |
Window lower bound register (WDT_WLB)¶
Offset: 0x0C
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | WDT_ WLB | 0x00000000 | R/W | Window lower bound register |
Window upper bound register (WDT_WUB)¶
Offset: 0x10
Reset value: 0xFFFFFFFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | WDT_ WUB | 0xFFFFFFFF | R/W | Window upper bound register |
Unlock Command Register (WDT_LOCK)¶
Offset: 0x14
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | WDT_ LOCK | 0x00000000 | R/W | Unlock command register: Write 0x51ACCE55 to this register to write all the other registers related to the module, otherwise you cannot write all the other registers When reading this register: 0x00000000: cannot write all other registers 0x00000001: can write all other registers |
Count value register (WDT_COUNT)¶
Offset: 0x18
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | WDT_ COUNT | 0x00000000 | RO | Count value register |
Status register (WDT_STATUS)¶
Offset: 0x1C
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:1 | Reserved | 0x00000000 | RO | Reserved |
| 0 | CNT_ EXT | 0 | RO | Count value count out of range status: 1: Exceeded upper limit 0: Not exceeded upper limit |