Independent Watchdog (IWTD)¶
Function introduction¶
Watchdog timer is a hardware timing circuit, which is mainly used to monitor whether the system has faults caused by abnormal software operation. The independent watchdog module is based on a 32-bit decrement counter and uses a clock independent of PCLK to count. When the counter decrements to 0, an interrupt request is generated. The counter overloads the initial value to decrement again. If the interrupt is not cleared before decrementing to 0, a reset request is generated and the counter stops counting. Both interrupt request and reset request can be enabled or disabled through the register. When the interrupt request is disabled, the counter stops counting. When the interrupt request is enabled again, the counter overloads the initial value to count down.
During software configuration, 0x1ACCE551 needs to be written to the lock register to access the remaining relevant registers.
Register Mapping¶
The base address of IWTD register mapping is 0x40032000, and the specific register mapping is shown in Table I-1.
| Offset | Name | Bit Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| 0x00 | WdogLoad | 32 | R/W | 0xFFFFFF | Initial count value register |
| 0x04 | WdogValue | 32 | RO | 0xFFFFFFFF | Count value register |
| 0x08 | WdogControl | 32 | R/W | 0x00000000 | Control register |
| 0x0C | WdogIntClr | 32 | WO | - | Interrupt clear register |
| 0x10 | WdogRIS | 32 | RO | 0x00000000 | Raw interrupt status register |
| 0x14 | WdogMIS | 32 | RO | 0x00000000 | Masking interrupt status register |
| 0xC00 | WdogLock | 32 | R/W | 0x00000000 | Lock register |
Count initial value register (WdogLoad)¶
Offset: 0x00
Reset value: 0xFFFFFFFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | WdogLoad | 0xFFFFFFFF | R/W | Initial count register |
Count Value Register (WdogValue)¶
Offset: 0x04
Reset value: 0xFFFFFFFF
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | WdogValue | 0xFFFFFFFF | R/W | Count value register |
Control register (WdogControl)¶
Offset: 0x08
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:2 | Reserved | 0x00000000 | R/W | Reserved |
| 1 | RESEN | 0 | R/W | Reset request enable: 0: Disable 1: Enable |
| 0 | INTEN | 0 | R/W | Interrupt request enable: 0: disable 1: enable |
Interrupt Clear Register (WdogIntClr)¶
Offset: 0x0C
Reset value:-
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:0 | WdogIntClr | - | WO | Interrupt clear register: Write any value to this register to clear the interrupt request. The counter overloads the initial value to count down. |
Raw Interrupt Status Register (WdogRIS)¶
Offset: 0x10
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:1 | Reserved | 0x00000000 | RO | Reserved |
| 0 | WdogRIS | 0 | RO | Original interrupt status |
Raw Interrupt Status Register (WdogRIS)¶
Offset: 0x14
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:1 | Reserved | 0x00000000 | RO | Reserved |
| 0 | WdogMIS | 0 | RO | Masking interrupt status |
Lock register (WdogLock)¶
Offset: 0xC00
Reset value: 0x00000000
| Bit Field | Name | Reset Value | Type | Description |
|---|---|---|---|---|
| 31:2 | WdogLock | 0x00000000 | R/W | Lock register: Write 0x1ACCE551 to this register to write all other registers related to the module, otherwise you cannot write all other registers When reading this register: 0x00000000: all other registers can be written 0x00000001: all other registers cannot be written |