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UART

Function introduction

The system chip has two UARTs: UART0 - UART1. The main features of the UART module are as follows:

  • Independent transmit FIFO and receive FIFO
  • Programmable baud rate, supporting DMA interface
  • Support standard UART protocol
  • Start bit error detection
  • Support parity
  • Data frames can be configured as 5, 6, 7, 8 bits
  • The stop bit can be configured as 1bit, 1.5bit and 2bit
  • Support the timeout interrupt mechanism, and the timeout size can be configured
  • The size of the FIFO is 64 * 8 bits, which supports FIFO overflow and underflow error detection
  • Support FIFO empty/full interrupt and transmission error interrupt
  • Up to 3M baud rate

Register Mapping

The base addresses of UART0/1 register mapping are 0x40022000 and 0x40023000 respectively. See Table U-1 for detailed register mapping.

Table U-1 UART Register Mapping

Offset Name Bit Width Type Reset Value Description
0x00 UART_ RdD_ R 32 RO 0x00000000 Read data register
0x04 UART_ WrD_ R 32 WO 0x00000000 Write data register
0x08 UART_ Rx_ Er_ R 32 R/W 0x00000000 Receive error flag register
0x0C UART_ Flag_ R 32 RO 0x0000034F Flag register
0x10 UART_ I_ BRD 32 R/W 0x00000000 Baud rate division counter integer part register
0x14 UART_ F_ BRD 32 R/W 0x00000000 Baud rate division counter fractional part register
0x18 UART_ LCR 32 RO 0x00000000 Linear control register
0x1C UART_ CR 32 RO 0x00000300 Control register
0x20 UART_ FLS 32 R/W 0x00000012 FIFO trigger depth configuration register
0x24 UART_ Mask_ Int 32 R/W 0x00000FFF Interrupt mask register
0x28 UART_ RIS 32 RO 0x00000020 Original interrupt status register
0x2C UART_ MIS 32 RO 0x00000000 Interrupt status register after shielding
0x30 UART_ ICR 32 WO 0x00000000 Interrupt clear register
0x34 UART_ DMA_ CR 32 R/W 0x00000000 DMA control register
0x38 UART_ TIMEOUT_ R 32 R/W 0x00000020 Receive delay register
0x50 UART_ DMA_ BYTE_ EN 32 R/W 0x00,000,000 DMA mode supports byte transmission

Read Data Register (UART_RdD_R)

Offset: 0x00

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:8 Reserved 0x000000 R Reserved
7:0 DATA 0x00 R Read DATA

Write Data Register (UART_WrD_R)

Offset: 0x04

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:0 WDATA 0x00000000 W 32-bit write data

Receive error flag register (UART_Rx_Er_R)

Offset: 0x08

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:4 Reserved 0x00000000 R/W Reserved
3 OE 0 R/W Overrun error flag
2 BE 0 R/W Break error flag
1 PE 0 R/W Parity error flag
0 FE 0 R/W Transmission Frame error flag

Flag register (UART_Flag_R)

Offset: 0x0C

Reset value: 0x0000034F

Bit Field Name Reset Value Type Description
31:11 Reserved 0x00000 R Reserved
10 Error Data Flag (EDF) 0 R When it is 1, it means that the error data in the current FIFO has not been read out, and the CPU should continue to output the data in the RXFIFO
9 End of current trans (EOC) 1 R Flag signal for completing the current transmission
8 Transmit FIFO Empty (TXFE) 1 R Transmit FIFO empty flag bit
7 Transmit FIFO Full (TXFF) 0 R Transmit FIFO full flag
6 Receive FIFO Empty (RXFE) 1 R Receive FIFO empty flag bit
5 Receive FIFO Full (RXFF) 0 R Receive FIFO full flag bit
4 UART Busy (BUSY) 0 R UART busy flag. When TXFIFO is not empty, the signal is 1
3: 1 Reversed - R Reserved
0 Clear To Send (CTS) 1 R When the CTS signal of the external modem is valid, the bit is 1

Integer part register of baud rate division counter (UART_I_BRD)

Offset: 0x10

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:0 Baud Rate Integer 0x00000000 R/W Integer part of baud rate division register

Baud rate division counter fractional part register (UART_F_BRD)

Offset: 0x14

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:6 Reserved 0x00000000 R/W Reserved
5: 0 Baud Rate Integer 0x00 R/W Baud rate fractional register

Linear control register (UART_LCR)

Offset: 0x18

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:6 Reserved 0x000000 R/W Reserved
8 Byte_ Select (BS) 0 R/W Write 1 to the bit, indicating that APB and AHB send data to TXFIFO in byte mode. When it is 0, it means to send data to TXFIFO in word mode.
7 Stick Parity Select (SPS) 0 R/W Fixed parity bit
6: 5 Word length [1:0] (WLEN) 0x0 R/W Number of valid data in each frame
00=5bit
01=6bit
10=7bit
11=8bit
4 FIFOs Clear (FIFO_CLR) 0 R/W Write 1 to the bit, and the FIFO will be cleared.
3: 2 Two Stop Bits Select (STP) 0x0 R/W Number of stop bits
00=1bit
01=1.5bit
10=2bit
11=reserved
1 Even Parity Select (EPS) 0 R/W Even parity selection. If it is 1, it is even parity; if it is 0, it is odd parity
0 Parity Enable (PEN) 0 R/W Parity check enable signal

Control register (UART_CR)

Offset: 0x1C

Reset value: 0x00000300

Bit Field Name Reset Value Type Description
31:16 Reserved 0x0000 R/W Reserved
15 CTS Hardware Flow Control Enable (CTSEn) 0 R/W The bit is written to 1. The hardware judges the CTS signal: continue to send data when the sampling is valid.
14 RTS Hardware Flow Control Enable (RTSEN) 0 R/W The bit is written to 1. The RTS signal is generated by the hardware. When RXFIFO does not reach the domain value, the RTS signal is always valid, and external data transmission is requested.
13 Out2 0 R/W When the bit writes 1, 0 is output on the output port nUARTOUT2. When used as a modem, this port can be used as a ring signal RI
12 Out1 0 R/W When the bit writes 1, 0 is output on the output port nUARTOUT1. When used as a modem, the port can be used as a data carrier detection signal DCD
11 Request to Send (RTS) 0 R/W This bit supplements the UART request to send (nUARTRTS) modem status output. When this bit is programmed to 1, the output is 0
10 Data Transmit Ready (DTR) 0 R/W This bit is a supplement to UART Data Transmission Ready (nUARTDTR) modem status output. When this bit is programmed to 1, the output is 0
9 Receive Enable (RXE) 1 R/W
8 Transmit Enable (TXE) 1 R/W When the bit bit is written to 1, it indicates that transmission is allowed. If it is disabled in the middle of a frame transmission, the current transmission should be completed first and then the transmission should be stopped
7: 2 Reversed 0 R/W Reserved
1 Don’t care error data (NCED) 0 R/W When the bit bit is written to 1, no matter whether RXFIFO has error data (parity error, frame error, break error, and overrun error), as long as RXFIFO reaches the domain value, it will send a DMA request or the CPU will receive an interrupt.
0 UART Enable (UARTEN) 0 R/W UART enable signal. When the bit is written to 1, it means enabled. If the UART is disabled in the middle of a transmission, the UART will not stop working until the current transmission is completed.

FIFO trigger depth configuration register (UART_FLS)

Offset: 0x20

Reset value: 0x00000012

Bit Field Name Reset Value Type Description
31:6 Reserved 0x000000 R/W Reserved
5:3 Receive Interrupt FIFO Level Select (RXIFLSEL) 0x2 R/W Receive FIFO trigger depth selection
000=Receive FIFO gains>=⅛ full
001=Receive FIFO gains>=¼ full
010=Receive FIFO gains>=½ full
011=Receive FIFO gains>=¾ full
100=Receive FIFO gains>=⅞ full
101=Receive FIFO is triggered as long as there is>=1 byte data in the Receive FIFO
110=Re If there are>=2 byte in the Receive FIFO,
111=reserved will be triggered
2: 0 Transmit Interrupt FIFO Level Select (TXIFLSEL) 0x2 R/W Transmit FIFO trigger depth selection
000=Transmit FIFO successes<⅛ full (spaces larger than ⅞ are empty)
001=Transmit FIFO successes<¼ full (spaces larger than ¾ are empty)
010=Transmit FIFO successes<½ full (spaces larger than ½ are empty)
011=Transmit FIFO successes<¾ full (spaces larger than ¼ are empty) Empty)
100=Transmit FIFO results<⅞ full (space larger than ⅛ is empty)
101:111=reserved

Interrupt mask register (UART_Mask_Int)

Offset: 0x24

Reset value: 0x00000FFF

Bit Field Name Reset Value Type Description
31:12 Reserved 0x00,000 R/W Reserved
11 Error data interrupt Mask (EDIM) 1 R/W Write 1 of this bit indicates that the error data interrupt is masked
10 Overrun Error Interrupt Mask (OEIM) 1 R/W Write 1 in this bit to indicate that Overrun Error Interrupt is masked
9 Break Error Interrupt Mask (BEIM) 1 R/W Writing 1 in this bit indicates that Break Error Interrupt is shielded
8 Parity Error Interrupt Mask (PEIM) 1 R/W Write 1 of this bit to indicate shielding Parity Error Interrupt
7 Framing Error Interrupt Mask (FEIM) 1 R/W Writing 1 in this bit indicates blocking Framing Error Interrupt
6 Receive Timeout Interrupt Mask (RTIM) 1 R/W Write 1 to this bit indicates that Receive Timeout Interrupt is shielded
5 Transmit Interrupt Mask (TXIM) 1 R/W Write 1 of this bit to indicate that Transmit Interrupt is shielded
4 Receive Interrupt Mask (RXIM) 1 R/W Write 1 in this bit to indicate that Receive Interrupt is shielded
3: 2 Reversed 0x3 R/W Reserved
1 nUARTCTS Modem Interrupt Mask (CTSMIM) 1 R/W Writing 1 in this bit indicates that the nUARTCTS Modem Interrupt is shielded
0 nUARTRI Modem Interrupt Mask (RIMIM) 1 R/W Writing 1 of this bit indicates that the nUARTRI Modem Interrupt is shielded

Raw Interrupt Status Register (UART_RIS)

Offset: 0x28

Reset value: 0x00000020

Bit Field Name Reset Value Type Description
31:12 Reserved 0x00,000 R/W Reserved
11 Error data interrupt status (EDRIS) 0 R/W Original error data interrupt status
10 Overrun Error Interrupt Status (OERIS) 0 R/W Original Overrun Error Interrupt Status
9 Break Error Interrupt Status (BERIS) 0 R/W Original Break Error Interrupt Status
8 Parity Error Interrupt Status (PERIS) 0 R/W Original Parity Error Interrupt Status
7 Framing Error Interrupt Status (FERIS) 0 R/W Original Framing Error Interrupt Status
6 Receive Timeout Interrupt Status (RTRIS) 0 R/W Original Receive Timeout Interrupt Status
5 Transmit Interrupt Status (TXRIS) 1 R/W Original Transmit Interrupt Status
4 Receive Interrupt Status (RXRIS) 0 R/W Original Receive Interrupt Status
3 nUARTDSR Modem Interrupt Status (DSRRMIS) 0 R/W Original nUARTDSR Modem Interrupt Status
2 nUARTDCD Modem Interrupt Status (DCDRMIS) 0 R/W Original nUARTDCD Modem Interrupt Status
1 nUARTCTS Modem Interrupt Status (CTSRMIS) 0 R/W Original nUARTCTS Modem Interrupt Status
0 nUARTRI Modem Interrupt Status (RIRMIS) 0 R/W Original nUARTRI Modem Interrupt Status

Masked Interrupt Status Register (UART_MIS)

Offset: 0x2C

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:12 Reserved 0x00000 R Reserved
11 Error data Masked interrupt Status (EDMIS) 0 R Error data interrupt status after shielding
10 Overrun Error Masked Interrupt Status (OEMIS) 0 R Overrun Error Interrupt status after shielding
9 Break Error Masked Interrupt Status (BEMIS) 0 R Break Error Interrupt status after shielding
8 Parity Error Masked Interrupt Status (PEMIS) 0 R Parity Error Interrupt status after shielding
7 Framing Error Masked Interrupt Status (FEMIS) 0 R Framing Error Interrupt status after shielding
6 Receive Timeout Masked Interrupt Status (RTMIS) 0 R Receive Timeout Interrupt status after shielding
5 Transmit Masked Interrupt Status (TXMIS) 0 R Transmit Interrupt status after shielding
4 Receive Masked Interrupt Status (RXMIS) 0 R Receive Interrupt status after shielding
3 nUARTDSR Modem Masked Interrupt Status (DSRMMIS) 0 R nUARTDSR Modem Interrupt status after shielding
2 nUARTDCD Modem Masked Interrupt Status (DCDMMIS) 0 R nUARTDCD Modem Interrupt status after shielding
1 nUARTCTS Modem Masked Interrupt Status (CTSMMIS) 0 R nUARTCTS Modem Interrupt status after shielding
0 nUARTRI Modem Masked Interrupt Status (RIMMIS) 0 R nUARTRI Modem Interrupt Status after shielding

Interrupt clear register (UART_ICR)

Offset: 0x30

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:12 Reserved 0x00000 W Reserved
11 Error data interrupt Clear (EDIC) 0 W Write 1 to the bit to clear the error data interrupt
10 Overrun Error Interrupt Clear (OEIC) 0 W Write 1 to the bit to clear Overrun Error Interrupt
9 Break Error Interrupt Clear (BEIC) 0 W Write 1 to the bit to clear Break Error Interrupt
8 Parity Error Interrupt Clear (PEIC) 0 W Write 1 to the bit to clear Parity Error Interrupt
7 Framing Error Interrupt Clear (FEIC) 0 W Write 1 to the bit to clear Framing Error Interrupt
6 Receive Timeout Interrupt Clear (RTIC) 0 W Write 1 to the bit to Clear Receive Timeout Interrupt
5 Transmit Interrupt Clear (TXIC) 0 W Write 1 to the bit to clear Transmit Interrupt
4 Receive Interrupt Clear (RXIC) 0 W Write 1 to the bit to clear Receive Interrupt
3 nUARTDSR Modem Interrupt Clear (DSRMIC) 0 W Write 1 to the bit to clear nUARTDSR Modem Interrupt
2 nUARTDCD Modem Interrupt Clear (DCDMIC) 0 W Write 1 to the bit to clear nUARTDCD Modem Interrupt
1 nUARTCTS Modem Interrupt Clear (CTSMIC) 0 W Write 1 to the bit to clear nUARTCTS Modem Interrupt
0 nUARTRI Modem Interrupt Clear (RIMIC) 0 W Write 1 to the bit to clear nUARTRI Modem Interrupt

DMA control register (UART_DMA_CR)

Offset: 0x34

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:12 Reserved 0x00000000 R/W Reserved
1 Transmit DMA Enable (TXDMAE) 0 R/W If this bit is set to 1, enable DMA request of transmit FIFO
0 Receive DMA Enable (RXDAE) 0 R/W If this bit is set to 1, enable receiving DMA request of FIFO

Receive delay register (UART_timeout_R)

Offset: 0x38

Reset value: 0x00000020

Bit Field Name Reset Value Type Description
31:10 Reserved 0x000000 R/W Reserved
9: 0 Timeout size (TS) 0x020 R/W Timeout delay size register. The default size is 32 baud bits. The maximum size is 1023 baud bits

DMA transfer mode control register (UART_DMA_BYTE_EN)

Offset: 0x50

Reset value: 0x00,000,000

Bit Field Name Reset Value Type Description
31:1 Reserved 0x00000000 R/W Reserved
0 EN 0x00 R/W When DMA mode transmission is used, the minimum transmission unit supported is BYTE, otherwise the minimum unit is WORD