General-Purpose Input/Output (GPIO)

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1. Introduction

• GPIO is a general-purpose input/output interface that allows the chip to interact with external hardware using logic-level signals. It can be configured as an input to receive external signals or as an output to control peripherals.

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2. Features

• CI13XX supports multiple programmable input/output pins. Each GPIO port has corresponding control and configuration registers. Each pin can be enabled or disabled individually, enabling precise control and status monitoring of external hardware. CI13XX provides 4 GPIO groups (GPIO0, GPIO1, GPIO2, GPIO3), mapped to chip ports PA, PB, PC, and PD respectively.

• GPIO supports input/output status querying, interrupt masking, interrupt clearing, and interrupt status querying. Configurable interrupt trigger types include low level, high level, rising edge, falling edge, and both edges to meet diverse application needs.

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3. API List

• The following APIs can configure one or multiple pins simultaneously

Function Name	Description
gpio_set_output_mode	Configure GPIO output mode
gpio_set_input_mode	Configure GPIO input mode
gpio_get_direction_status	Get GPIO pin direction
gpio_irq_mask	Mask GPIO interrupt
gpio_irq_unmask	Unmask GPIO interrupt
gpio_irq_trigger_config	Configure GPIO interrupt trigger type
gpio_set_output_high_level	Set GPIO output high level
gpio_set_output_low_level	Set GPIO output low level
gpio_get_input_level	Get GPIO input level

• The following APIs configure a single pin

Function Name	Description
gpio_get_direction_status_single	Get direction of a single pin
gpio_get_irq_raw_status_single	Get pre-mask interrupt status of a single pin
gpio_get_irq_mask_status_single	Get post-mask interrupt status of a single pin
gpio_clear_irq_single	Clear interrupt for a single pin
gpio_set_output_level_single	Control output level of a single pin
gpio_get_input_level_single	Read input level of a single pin

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4. Special Notes

• Pins PA0 and PA1 are connected to the crystal oscillator and are analog by default.

• Pins PC1, PC2, PC3, and PC4 are analog by default.

• These analog-function pins require special configuration when used as GPIO. The following sections provide examples for General I/O, Crystal Oscillator I/O, and Analog I/O.

5. General I/O Examples

5.1 General I/O Output Mode

• The following code configures PB group pin 4 as output mode

#include "ci130x_scu.h"
#include "ci130x_dpmu.h"
#include "ci130x_gpio.h"

void gpio_output_test()
{
    /* PB group GPIO controller clock configuration */
    scu_set_device_gate((unsigned int)PB,ENABLE);        // Enable PB clock

    /* PB4 pin initialization */
    dpmu_set_io_reuse(PB4,FIRST_FUNCTION);               // Set pin function to GPIO
    dpmu_set_io_direction(PB4,DPMU_IO_DIRECTION_OUTPUT); // Configure pin as output
    dpmu_set_io_pull(PB4,DPMU_IO_PULL_DISABLE);          // Disable internal pull-up/down

    /* Configure PB pin_4 as GPIO output */
    gpio_set_output_mode(PB,pin_4);                      // Set pin as output

    /* PB pin_4 output level */
    gpio_set_output_level_single(PB,pin_4,0);            // Output low level
    gpio_set_output_level_single(PB,pin_4,1);            // Output high level
}

5.2 General I/O Open-Drain Output Mode

• The following code configures PB group pin 4 as open-drain output

#include "ci130x_scu.h"
#include "ci130x_dpmu.h"
#include "ci130x_gpio.h"

void gpio_open_drain_output_test()
{
    /* PB group GPIO controller clock configuration */
    scu_set_device_gate((unsigned int)PB,ENABLE);       // Enable PB clock

    /* PB4 pin initialization, enable open-drain */
    dpmu_set_io_reuse(PB4,FIRST_FUNCTION);              // Set pin function to GPIO
    dpmu_set_io_open_drain(PB4,ENABLE);                 // Enable open-drain; supports external 5V pull-up
    dpmu_set_io_pull(PB4,DPMU_IO_PULL_DISABLE);         // Disable pull-up
    dpmu_set_io_direction(PB4,DPMU_IO_DIRECTION_OUTPUT);// Configure pin as output

    /* Configure PB pin_4 as GPIO output */
    gpio_set_output_mode(PB,pin_4);                     // Set pin as output

    /* PB pin_4 output level */
    gpio_set_output_level_single(PB,pin_4,0);            // Output low level
    gpio_set_output_level_single(PB,pin_4,1);            // Output high level
}

5.3 General I/O Input Mode

• The following code configures PB group pin 4 as input mode

#include "ci130x_scu.h"
#include "ci130x_dpmu.h"
#include "ci130x_gpio.h"

void gpio_input_test()
{
    /* PB group GPIO controller clock configuration */
    scu_set_device_gate((unsigned int)PB,ENABLE);       // Enable PB clock

    /* PB4 pin initialization */
    dpmu_set_io_reuse(PB4,FIRST_FUNCTION);              // Set pin function to GPIO
    dpmu_set_io_direction(PB4,DPMU_IO_DIRECTION_INPUT); // Configure pin as input
    dpmu_set_io_pull(PB4,DPMU_IO_PULL_DISABLE);         // Disable internal pull-up/down

    /* Configure PB pin_4 as GPIO input */
    gpio_set_input_mode(PB,pin_4);                      // Set pin as input

    /* Read input level of PB pin_4 */
    if(0 == gpio_get_input_level_single(PB,pin_4))      // Get IO level
    {
        // INFO: input is low level
    }
    else
    {
        // INFO: input is high level
    }
}

5.4 General I/O Interrupt Mode

• The following code configures PB group pin 4 to trigger interrupts on both edges

#include "ci130x_scu.h"
#include "ci130x_dpmu.h"
#include "ci130x_gpio.h"
#include "ci130x_core_eclic.h"

void gpio_interrupt_test()
{
    /* PB group GPIO controller clock configuration */
    scu_set_device_gate((unsigned int)PB,ENABLE);          // Enable PB clock

    /* PB4 pin initialization */
    dpmu_set_io_reuse(PB4,FIRST_FUNCTION);                 // Set pin function to GPIO
    dpmu_set_io_direction(PB4,DPMU_IO_DIRECTION_INPUT);    // Configure pin as input
    dpmu_set_io_pull(PB4,DPMU_IO_PULL_DISABLE);            // Disable internal pull-up/down

    /* Configure PB pin_4 as GPIO input and enable interrupts */
    gpio_set_input_mode(PB,pin_4);                         // Set pin as input
    gpio_irq_trigger_config(PB,pin_4,both_edges_trigger);  // Configure interrupt trigger
    eclic_irq_enable(PB_IRQn);                             // Enable interrupt
}

/* The PB interrupt service routine is defined in ci130x_gpio.c as */
//void PB_IRQHandler(void);

Warning

IOs in groups PA, PB, and PC support input, output, and interrupt functions. Group PD supports only input and output; interrupts are not available.

6. Crystal Oscillator I/O Examples

Pins PA0 and PA1 are connected to the crystal oscillator and are analog by default. To use them as GPIO, disable the oscillator function first and then configure them as digital.

6.1 Crystal Oscillator I/O Output Mode

• The following code configures PA0 in group PA as output. PA1 can follow the same configuration.

#include "ci130x_scu.h"
#include "ci130x_dpmu.h"
#include "ci130x_gpio.h"

void gpio_output_test()
{
    /* Enable crystal oscillator pins for GPIO */
    dpmu_osc_pad_for_gpio(ENABLE);              // To use PA0/PA1 as GPIO, the oscillator must be disabled

    /* PA group GPIO controller clock configuration */
    scu_set_device_gate(PA,ENABLE);             // Enable PA clock

    /* PA0 pin initialization */
    dpmu_set_io_reuse(PA0,FIRST_FUNCTION);      // Initialize as GPIO function
    dpmu_set_adio_reuse(PA0,DIGITAL_MODE);      // Initialize as digital; default is analog
    dpmu_set_io_direction(PA0,DPMU_IO_DIRECTION_OUTPUT);  // Configure pin as output

    /* Configure PA pin_0 as GPIO output */
    gpio_set_output_mode(PA,pin_0);             // Set PA pin_0 to output mode

    /* PA pin_0 output level */
    gpio_set_output_high_level(PA,pin_0);       // Output high level
    gpio_set_output_low_level(PA,pin_0);        // Output low level
}

6.2 Crystal Oscillator I/O Input Mode

• The following code configures PA0 in group PA as input. PA1 can follow the same configuration.

#include "ci130x_scu.h"
#include "ci130x_dpmu.h"
#include "ci130x_gpio.h"

void gpio_input_test()
{
    /* Enable crystal oscillator pins for GPIO */
    dpmu_osc_pad_for_gpio(ENABLE);              // To use PA0/PA1 as GPIO, the oscillator must be disabled

    /* PA group GPIO controller clock configuration */
    scu_set_device_gate(PA,ENABLE);             // Enable PA clock

    /* PA0 pin initialization */
    dpmu_set_io_reuse(PA0,FIRST_FUNCTION);      // Initialize as GPIO function
    dpmu_set_adio_reuse(PA0,DIGITAL_MODE);      // Initialize as digital; default is analog
    dpmu_set_io_direction(PA0,DPMU_IO_DIRECTION_INPUT);  // Configure pin as input

    /* Configure PA pin_0 as GPIO input */
    gpio_set_input_mode(PA,pin_0);              // Initialize PA pin_0 as input

    /* Read input level of PA pin_0 */
    if(0 == gpio_get_input_level_single(PA,pin_0)) // Get IO level
    {
        // INFO: input is low level
    }
    else
    {
        // INFO: input is high level
    }
}

6.3 Crystal Oscillator I/O Interrupt Mode

The following code configures PA0 in group PA to trigger interrupts on both edges. PA1 can follow the same configuration.

#include "ci130x_scu.h"
#include "ci130x_dpmu.h"
#include "ci130x_gpio.h"
#include "ci130x_core_eclic.h"

void gpio_interrupt_test()
{
    /* Enable crystal oscillator pins for GPIO */
    dpmu_osc_pad_for_gpio(ENABLE);              // To use PA0/PA1 as GPIO, the oscillator must be disabled

    /* PA group GPIO controller clock configuration */
    scu_set_device_gate(PA,ENABLE);             // Enable PA clock

    /* PA0 pin initialization */
    dpmu_set_io_reuse(PA0,FIRST_FUNCTION);      // Initialize as GPIO function
    dpmu_set_adio_reuse(PA0,DIGITAL_MODE);      // Initialize as digital; default is analog
    dpmu_set_io_direction(PA0,DPMU_IO_DIRECTION_INPUT);  // Configure pin as input

    /* Configure PA pin_0 as GPIO input and enable interrupt */
    gpio_set_input_mode(PA,pin_0);              // Initialize PA pin_0 as input
    gpio_irq_trigger_config(PA,pin_0,both_edges_trigger);  // Configure interrupt trigger
    eclic_irq_enable(PA_IRQn);                  // Enable interrupt

    /* The PA interrupt service routine is defined in ci130x_gpio.c as */
    //void PA_IRQHandler(void);
}

7. Analog I/O Examples

Pins PC1, PC2, PC3, and PC4 are analog by default. To use them as GPIO, configure them as digital.

7.1 Analog I/O Output Mode

• The following code configures PC1 in group PC as output mode

#include "ci130x_scu.h"
#include "ci130x_dpmu.h"
#include "ci130x_gpio.h"

void gpio_output_test()
{
    /* PC group GPIO controller clock configuration */
    scu_set_device_gate(PC,ENABLE);             // Enable PC clock

    /* PC1 pin initialization */
    dpmu_set_io_reuse(PC1,FIRST_FUNCTION);      // Initialize as GPIO function
    dpmu_set_adio_reuse(PC1,DIGITAL_MODE);      // Initialize as digital; default is analog
    dpmu_set_io_direction(PC1,DPMU_IO_DIRECTION_OUTPUT);  // Configure pin as output

    /* Configure PC pin_1 as GPIO output */
    gpio_set_output_mode(PC,pin_1);             // Initialize PC pin_1 as output

    /* PC pin_1 output level */
    gpio_set_output_high_level(PC,pin_1);       // Output high level
    gpio_set_output_low_level(PC,pin_1);        // Output low level
}

7.2 Analog I/O Input Mode

• The following code configures PC1 in group PC as input mode

#include "ci130x_scu.h"
#include "ci130x_dpmu.h"
#include "ci130x_gpio.h"

void gpio_input_test()
{
    /* PC group GPIO controller clock configuration */
    scu_set_device_gate(PC,ENABLE);             // Enable PC clock

    /* PC1 pin initialization */
    dpmu_set_io_reuse(PC1,FIRST_FUNCTION);      // Initialize as GPIO function
    dpmu_set_adio_reuse(PC1,DIGITAL_MODE);      // Initialize as digital; default is analog
    dpmu_set_io_direction(PC1,DPMU_IO_DIRECTION_INPUT);  // Configure pin as input

    /* Configure PC pin_1 as GPIO input */
    gpio_set_input_mode(PC,pin_1);              // Initialize PC pin_1 as input

    /* Read input level of PC pin_1 */
    if(0 == gpio_get_input_level_single(PC,pin_1))       // Get IO level
    {
        // INFO: input is low level
    }
    else
    {
        // INFO: input is high level
    }
}

7.3 Analog I/O Interrupt Mode

• The following code configures PC1 in group PC to trigger interrupts on both edges

#include "ci130x_scu.h"
#include "ci130x_dpmu.h"
#include "ci130x_gpio.h"
#include "ci130x_core_eclic.h"

void gpio_interrupt_test()
{
    /* PC group GPIO controller clock configuration */
    scu_set_device_gate(PC,ENABLE);             // Enable PC clock

    /* PC1 pin initialization */
    dpmu_set_io_reuse(PC1,FIRST_FUNCTION);      // Initialize as GPIO function
    dpmu_set_adio_reuse(PC1,DIGITAL_MODE);      // Initialize as digital; default is analog
    dpmu_set_io_direction(PC1,DPMU_IO_DIRECTION_INPUT);  // Configure pin as input

    /* Configure PC pin_1 as GPIO input and enable interrupt */
    gpio_set_input_mode(PC,pin_1);              // Initialize PC pin_1 as input
    gpio_irq_trigger_config(PC,pin_1,both_edges_trigger);  // Configure interrupt trigger
    eclic_irq_enable(PC_IRQn);                  // Enable interrupt

    /* The PC interrupt service routine is defined in ci130x_gpio.c as */
    //void AON_PC_IRQHandler(void);
}

8. API Reference