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Hardware Design

The CI13322 chip requires minimal external components to develop end-product solutions supporting various voice applications. The chip supports both differential and single-ended microphone inputs. The application design can be tailored based on functional requirements, power consumption, cost, and other factors to select the most suitable circuit design.

This section uses the typical application solution of CI13322 as an example to introduce key points and considerations for application design:

Reference Circuit Diagram

Figure H-1 Typical Application Reference Circuit

The above figure shows the reference design circuit diagram of a typical application solution for the CI13322 chip with single-microphone differential input and power amplifier output. This design is not limited to any specific end product. The application design should be based on the principle of adapting to the host terminal product. According to the functional and performance requirements of the terminal product, please visit the Chipintelli Documentation Center and AI platform to download reference schematics and PCB layouts. Documentation Center link: https://document.Chipintelli.com/.

If board-level upgrade functionality needs to be reserved in the application design, the UART0 pins can be brought out via connectors or test points to facilitate firmware programming or upgrading through UART0 after PCB assembly.

The PA4 (PG_EN) pin of CI13322 has an internal 3.3V pull-up resistor. During power-on, the system detects whether this pin is pulled high to 3.3V. If it is high and an upgrade signal is detected on the UART0 pins, the system enters upgrade mode. If this pin is externally pulled down to ground, the system can skip the upgrade mode detection and directly enter normal startup mode for faster boot-up. For applications requiring fast boot-up, the PA4 pin can be brought out and connected in series with two 2.2KΩ pull-down resistors to ground, with a test point between the two resistors (for specific implementation, please refer to the reference application diagram or consult our FAE). In this design, the system will boot in normal functional mode with a startup time of approximately 350ms. If an online upgrade is needed, a 3.3V high level can be applied to the test point between the two 2.2KΩ resistors to pull the PA4 pin high, enabling upgrade via the UART0 port.

CI13322 supports both differential and single-ended microphone inputs, with the differential microphone design shown in Figure H-1 being the recommended approach. For cost-sensitive designs, a single-ended microphone input can be used to reduce component count on the microphone input line. However, this approach is only recommended for microphone input lines shorter than 20cm, as longer lines may affect noise immunity and degrade voice recognition performance.

The power amplifier in this typical application is configured as a Class AB amplifier, with the 8002 series being recommended. If voice prompt functionality is not required, this circuit section can be removed to reduce costs.

If the application does not have ultra-low power consumption requirements, it is recommended to use the internal PMU of CI13322 for power supply to reduce costs. For applications requiring ultra-low power consumption, an external DCDC circuit can be used to supply 1.1V to CI13322 to reduce system power consumption.

All UART ports of CI13322 support 5V level communication. In the figure above, UART0 is shown with 3.3V communication level as an example. If 5V communication level is required, 5V pull-up resistors can be added to the RX and TX pins of UART0 without the need for level conversion circuits.

PCB Layout Design

Power Circuit

Power Routing

Pay attention to overvoltage protection and surge protection for power input. Design TVS devices and 4.7Ω resistors at the 5V input, with the trace passing through the TVS first, then the resistor before reaching the chip. The width of power traces should be determined based on the actual circuit current. For 3.3V power, the trace width should be no less than 15mil, and for 1.1V power, no less than 15mil. Use copper pour for power routing when possible, keeping traces as short and wide as possible, with the narrowest point no less than 8mil. Avoid forming closed loops in power traces.

Power Decoupling Capacitors

Place power decoupling capacitors as close as possible to their corresponding pins.

ESD Protection Requirements

For two-layer board designs, try to route traces on the TOP layer to maintain the integrity of the BOTTOM ground plane. If ESD protection devices are included in the design, place them as close as possible to the connector pins to improve protection effectiveness.

Additional Application Notes

1. CI13322 is manufactured with lead-free, environmentally friendly materials. When performing SMT soldering, please set the reflow temperature and time parameters according to lead-free standards. A typical SMT soldering temperature profile is shown below:

   

   Figure H-2 Chip SMT Soldering Temperature Profile

2. Anti-static measures must be taken during handling, transportation, and processing of CI13322. Use anti-static packaging materials.

3. The chip has a moisture sensitivity level (MSL) of 3. Please store it under MSL3 conditions before use. If the package has been opened for longer than the MSL3 requirement, please bake the chips before SMT soldering.