Serial Flash Controller (SPIFLASH)¶
Introduction¶
The SPIFLASH controller is a Chipintelli‑developed module (qspi_controller), different from common SPI controllers on the market. It provides unique features, including: AMBA 2.0 compliance; APB configuration and AHB data transfer; 32‑bit data width only; DMA transfer support; CPU boot transfer; SINGLE mode transfer; support for SINGLE/INCR/INCR4/INCR8/INCR16 burst types; dual AHB data buses; PARA parameter prefetch and normal operations; configurable M value; 64‑deep × 32‑bit TX/RX FIFOs; write/erase address protection; pin‑level FLASH reset; AHB bus detection on AHB0; configurable waterline; DMA read/write with single and burst requests. Except for boot mode, each read/write requires APB‑side configuration (transfer mode, size, start address, etc.) beforehand.
API List¶
| Function Name | Description |
|---|---|
| flash_init | Initialize SPIFLASH device |
| spic_read_unique_id | Read SPIFLASH UNIQUE ID |
| spic_read_jedec_id | Read SPIFLASH JEDEC ID |
| spic_erase_security_reg | Erase SPIFLASH security register |
| spic_write_security_reg | Write SPIFLASH security register |
| spic_read_security_reg | Read SPIFLASH security register |
| spic_security_reg_lock | Lock SPIFLASH security register |
| flash_erase | Erase SPIFLASH |
| flash_write | Write SPIFLASH |
| flash_read | Read SPIFLASH |
| spic_quad_mode | Set SPIFLASH Quad mode |
Example¶
The following example initializes FLASH, checks mode, and then performs erase/write/read operations:
#include "ci130x_spiflash.h"
#include "ci_log.h"
uint8_t write_buf[1024] = {0}; /* Buffer for data to write to FLASH */
uint8_t read_buf[1024] = {0}; /* Buffer for data read from FLASH */
void flash_test()
{
uint32_t flash_addr = 0x10000; /* FLASH offset address */
uint32_t size = 256; /* Read/Write size */
for(int i=0; i<size; i++)
{
write_buf[i] = i;
read_buf[i] = 0;
}
/* Initialize FLASH */
if(RETURN_OK != flash_init(QSPI0))
{
mprintf("flash init error !!!\n");
while(1);
}
/* FLASH erase 4K */
if(RETURN_OK != flash_erase(QSPI0,flash_addr,(4 * 1024)))
{
mprintf("flash erase error !!!\n");
while(1);
}
/* FLASH write data */
if(RETURN_OK != flash_write(QSPI0,flash_addr,write_buf,size))
{
mprintf("flash write error !!!\n");
while(1);
}
/* FLASH read data */
if(RETURN_OK != flash_read(QSPI0,read_buf,flash_addr,size))
{
mprintf("flash read error !!!\n");
while(1);
}
/* Compare written and read data */
if(memcmp(write_buf, read_buf, size))
{
mprintf("cmp error !!!\n");
while(1);
}
else
{
// Comparison correct
}
}