Hardware Design¶
The CI1316X chip requires minimal external components to develop end-product solutions supporting various voice applications. The chip supports single microphone with either differential or single-ended input. The application design can be tailored based on functional requirements, power consumption, and cost considerations.
The following sections outline the key points and considerations for application design, using the CI13162 typical application as an example:
Application Reference Circuit¶
The above diagram shows the reference design schematic for the CI1316X series chips (including CI13162), featuring single microphone differential input and power amplifier output. This design is not limited to any specific end product. Application designs should follow the principle of adapting to host terminal products. For reference schematics and PCB layouts based on functional and performance requirements, please visit the Chipintelli Documentation Center and AI Platform at: https://document.Chipintelli.com/.
For designs requiring board-level upgrade functionality, the UART0 pins can be exposed via connectors or test points to facilitate firmware programming or upgrades after PCB assembly.
The PA4 (PG_EN) pin of CI13162 has an internal 3.3V pull-up resistor. During power-up, the system checks if this pin is pulled high to 3.3V. If it is high and an upgrade signal is detected on the UART0 pins, the system enters upgrade mode. If the pin is externally pulled down to ground, the system skips the upgrade mode detection and boots directly into normal operation for faster startup.
For applications requiring fast startup, the PA4 pin can be configured with two 2.2KΩ pull-down resistors in series to ground, with a test point between them (refer to the reference schematic or consult our FAE for specific implementation). In this configuration, the system boots in normal mode with a startup time of approximately 350ms. For in-circuit upgrades, applying 3.3V to the test point between the two 2.2KΩ resistors will pull PA4 high, enabling Firmware Updates via UART0. The two operating modes of PG_EN are shown in the table below:
| PG_EN External Resistor Diagram | R5\R6 Configuration | PG_EN Level | Boot Time |
|---|---|---|---|
 |
R5\R6 Not Populated | High, Upgrade Mode | 850ms |
 |
R5\R6 = 2.2KΩ | Low, Normal Mode | 350ms |
CI13162 supports both differential and single-ended microphone inputs. The differential microphone design shown in Figure H-1 is recommended. For cost-sensitive designs, a single-ended microphone input can be used to reduce component count, but this is only recommended when the microphone input trace length is less than 20cm. Longer traces may reduce noise immunity and degrade voice recognition performance.
This reference design uses a Class AB power amplifier, with the 8002 series recommended. The amplifier circuit can be omitted if voice playback functionality is not required, reducing overall solution cost.
For applications without ultra-low power requirements, using the internal PMU of CI13162 is recommended to minimize cost. For applications requiring ultra-low power consumption, an external DCDC converter can be used to supply 1.1V to the CI13162, reducing system power consumption.
The UART interfaces on CI13162 support 5V level communication. While the UART0 interface in the diagram shows 3.3V level communication, 5V level communication can be achieved by adding 5V pull-up resistors to the RX and TX pins of UART0, eliminating the need for level-shifting circuitry.
PCB Layout Design¶
Power Supply Circuit¶
Power Traces¶
Implement overvoltage and surge protection for power inputs. Include TVS devices and 4.7Ω resistors in the 5V input path, with the TVS placed before the resistor. Power trace width should be determined by the actual current requirements, with minimum widths of 15mil for 3.3V and 1.1V power rails. Use copper pours for power distribution when possible, keeping traces short and wide. The minimum trace width should not be less than 8mil at any point, and avoid creating closed loops in power traces.
Power Decoupling Capacitors¶
Place power decoupling capacitors as close as possible to their corresponding pins.
ESD Protection Requirements¶
For two-layer board designs, route traces primarily on the TOP layer to maintain the integrity of the BOTTOM ground plane. When ESD protection devices are used, position them as close as possible to the connector pins to maximize protection effectiveness.
Additional Application Notes¶
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CI1316X is manufactured using lead-free materials. When performing SMT soldering, please follow lead-free profile standards for temperature and time parameters. A typical SMT reflow temperature profile is shown below:
Figure H-2 Chip SMT Reflow Temperature Profile -
Proper ESD protection measures must be observed during handling, transportation, and production of CI1316X. Use anti-static packaging materials at all times.
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The Moisture Sensitivity Level (MSL) of the chip is MSL3. Store the device under MSL3 conditions before use. If the device has been exposed to ambient conditions for longer than the MSL3 specified duration, baking is required prior to SMT assembly.