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Hardware Design

The CI2324X chip requires minimal external components to develop end-product solutions supporting various voice applications. The chip supports single microphone with either differential or single-ended input. The application design can be tailored based on functional requirements, power consumption, and cost considerations.

Using the CI23242 typical application as an example, this section outlines key design considerations and precautions:

Reference Circuit Diagram

Figure H-1 Typical Application Reference Circuit

The above diagram shows the reference design schematic for the CI2324X series chips (including CI23242), featuring single microphone differential input and power amplifier output. This design is not limited to any specific end product. Application designs should be based on the principle of compatibility with host terminal products. For reference schematics and PCB layout tailored to your product’s functional and performance requirements, please visit the Chipintelli Documentation Center and AI Platform: https://document.Chipintelli.com/.

For designs requiring board-level upgrade functionality, the UART0 pins can be made accessible via connectors or test points, facilitating firmware programming or updates after PCB assembly.

The PA4 (PG_EN) pin of CI23242 has an internal 3.3V pull-up resistor. During power-up, the system checks if this pin is pulled high to 3.3V. If high and an upgrade signal is detected on the UART0 pins, the system enters upgrade mode. If the pin is externally pulled low, the system skips the upgrade mode detection and boots directly to normal operation mode for faster startup. For applications requiring fast startup, route the PA4 pin through two 2.2KΩ pull-down resistors to ground, with a test point between them (refer to the reference schematic or consult our FAE for implementation details). In this configuration, the system boots in normal mode with a startup time of approximately 350ms. For in-circuit upgrades, apply 3.3V to the test point between the two 2.2KΩ resistors to pull PA4 high, enabling UART0-based upgrades. The two operating modes of PG_EN are shown in the table below:

PG_EN External Resistor Diagram	R5\R6 Configuration	PG_EN Level	Boot Time
	R5\R6 Not Populated	High, Upgrade Mode	850ms
	R5\R6 = 2.2KΩ	Low, Normal Mode	350ms

CI23242 supports both differential and single-ended microphone inputs. The differential microphone design shown in Figure H-1 is recommended. For cost-sensitive designs, a single-ended microphone input can be used to reduce component count, but this is only recommended for microphone input trace lengths under 20cm. Longer traces may reduce noise immunity and degrade voice recognition performance.

The reference design uses a Class AB power amplifier, with the 8002 series recommended. The amplifier circuit can be omitted if voice playback functionality is not required, reducing overall solution cost.

For applications without ultra-low power requirements, using the internal PMU of CI23242 is recommended to reduce cost. For ultra-low power applications, an external DCDC converter can be used to supply 1.1V to the CI23242 to minimize system power consumption.

CI23242’s UART interfaces support 5V level communication. For 5V communication, simply add 5V pull-up resistors to the UART0 RX and TX pins; no level-shifting circuit is required.

The crystal oscillator specification for CI23242 is 24MHz with a load capacitance (CL) of 9pF and matching capacitors of 10pF. These parameters must not be changed.

For antenna design, refer to the Chipintelli reference design. The matching capacitor should use the recommended values and be placed as close as possible to the RF pin. The PCB antenna area should be kept clear with an intact reference plane, away from metal components to avoid affecting antenna performance.

PCB Layout Design

Power Circuit

Power Traces

Implement over-voltage and surge protection for the power input by including TVS devices and 1Ω resistors on the 5V input line. The power trace should first pass through the TVS device, then the resistor before reaching the chip. Power trace width should be determined by the actual current requirements: at least 15 mils for 3.3V power traces and 15 mils for 1.1V power traces. Use copper pours where possible, keeping power traces short and wide, with a minimum width of 8 mils at the narrowest point. Avoid creating closed loops in power traces.

Power Decoupling Capacitors

Place power decoupling capacitors as close as possible to their respective pins.

ESD Protection Requirements

For two-layer board designs, route traces primarily on the TOP layer to maintain a solid ground plane on the BOTTOM layer. When ESD protection devices are used, place them as close as possible to the connector pins for optimal protection.

Additional Application Notes

1. CI2324X is manufactured using lead-free, environmentally friendly materials. When performing SMT soldering, please follow lead-free soldering profiles for temperature and time parameters. A typical SMT reflow profile is shown below:

   

   Figure H-2 Chip SMT Reflow Profile

2. Proper ESD precautions must be observed during handling, transportation, and processing of CI2324X. Use ESD-safe packaging materials.

3. The chip has a Moisture Sensitivity Level (MSL) of 3. Store under MSL3 conditions before use. If the package has been exposed to ambient conditions beyond the MSL3 time limit, bake the components before SMT soldering.