General-Purpose Input/Output (GPIO)¶

Introduction¶

Each GPIO port has corresponding control and configuration registers. The API is divided into two categories: one for operating a single pin, and another for operating one or more pins simultaneously. It provides interfaces for querying I/O status, interrupt masking, interrupt status querying, interrupt clearing, and interrupt trigger configuration (configurable as: low-level trigger, high-level trigger, rising edge trigger, falling edge trigger, or both-edge trigger) to meet various application requirements.

The CI13LC series chips currently have 3 groups of GPIOs: PA, PB, and PC. For the pin definitions of each group, please refer to ci13642.h.

API Reference¶

The following APIs can set one or more pins simultaneously:

Function Name	Description
gpio_set_output_mode	Configure GPIO output mode
gpio_set_input_mode	Configure GPIO input mode
gpio_get_direction_status	Get GPIO direction
gpio_irq_mask	Mask GPIO interrupt
gpio_irq_unmask	Unmask GPIO interrupt
gpio_irq_trigger_config	Configure GPIO interrupt trigger mode
gpio_set_output_high_level	Set GPIO output high level
gpio_set_output_low_level	Set GPIO output low level
gpio_get_input_level	Get GPIO input level

The following APIs are used to configure a single pin:

Function Name	Description
gpio_get_direction_status_single	Get I/O direction of a single pin
gpio_get_irq_raw_status_single	Get pre-mask interrupt status of a pin
gpio_get_irq_mask_status_single	Get post-mask interrupt status of a pin
gpio_clear_irq_single	Clear interrupt for a single pin
gpio_set_output_level_single	Control output level of a single pin
gpio_get_input_level_single	Get input level of a single pin

Special Notes¶

Pins PA0 and PA1 are connected to the crystal oscillator by default and are in analog mode. Their configuration is different from other I/Os. The following examples are divided into [Normal I/O Examples] and [Crystal I/O Examples].

Normal I/O Examples¶

The following code controls pin 4 of the PB group in output mode:

scu_set_device_gate((unsigned int)PA, ENABLE);        // Enable PB clock
dpmu_set_io_reuse(PA7, FIRST_FUNCTION);               // Set pin function to GPIO
dpmu_set_io_direction(PA7, DPMU_IO_DIRECTION_OUTPUT); // Set pin as output mode
dpmu_set_io_pull(PA7, DPMU_IO_PULL_DISABLE);          // Disable pull-up/down
gpio_set_output_mode(PA, pin_7);                      // Configure GPIO pin as output mode
gpio_set_output_level_single(PA, pin_7, 0);            // Output low level
gpio_set_output_level_single(PA, pin_7, 1);            // Output high level

The following code configures pin 4 of the PB group as open-drain output mode:

scu_set_device_gate((unsigned int)PA, ENABLE);       // Enable PB clock
dpmu_set_io_reuse(PA7, FIRST_FUNCTION);              // Set pin function to GPIO
dpmu_set_io_open_drain(PA7, ENABLE);                 // Configure pin as open-drain, supports 5V external pull-up
dpmu_set_io_pull(PA7, DPMU_IO_PULL_DISABLE);         // Disable pull-up
dpmu_set_io_direction(PA7, DPMU_IO_DIRECTION_OUTPUT);// Set pin as output mode
gpio_set_output_mode(PA, pin_7);                     // Configure GPIO pin as output mode

The following code configures I2C pins (PA2/PA3) as open-drain output mode:

dpmu_set_io_reuse(PA2, THIRD_FUNCTION);              // Set pin function to I2C
dpmu_set_io_reuse(PA3, THIRD_FUNCTION);              // Set pin function to I2C
dpmu_set_io_open_drain(PA2, ENABLE);                 // Configure pin as open-drain, supports 5V external pull-up
dpmu_set_io_open_drain(PA3, ENABLE);                 // Configure pin as open-drain, supports 5V external pull-up
dpmu_set_io_pull(PA2, DPMU_IO_PULL_DISABLE);         // Disable pull-up
dpmu_set_io_pull(PA3, DPMU_IO_PULL_DISABLE);         // Disable pull-up
dpmu_set_io_direction(PA3, DPMU_IO_DIRECTION_OUTPUT);// Configure SCL as output

The following code configures pin 4 of the PB group as input mode:

scu_set_device_gate((unsigned int)PA, ENABLE);       // Enable PB clock
dpmu_set_io_reuse(PA7, FIRST_FUNCTION);              // Set pin function to GPIO
dpmu_set_io_direction(PA7, DPMU_IO_DIRECTION_INPUT); // Set pin as input mode
dpmu_set_io_pull(PA7, DPMU_IO_PULL_DISABLE);         // Disable pull-up/down
gpio_set_input_mode(PA, pin_7);                      // Configure GPIO pin as input mode
if (0 == gpio_get_input_level_single(PA, pin_7)) {   // Get I/O level
    // INFO: Input is low level
} else {
    // INFO: Input is high level
}

The following code configures pin 4 of the PB group for both-edge triggered interrupt:

scu_set_device_gate((unsigned int)PA, ENABLE);          // Enable PB clock
dpmu_set_io_reuse(PA7, FIRST_FUNCTION);                 // Set pin function to GPIO
dpmu_set_io_direction(PA7, DPMU_IO_DIRECTION_INPUT);    // Set pin as input mode
dpmu_set_io_pull(PA7, DPMU_IO_PULL_DISABLE);            // Disable pull-up/down
gpio_set_input_mode(PA, pin_7);                         // Configure GPIO pin as input mode
gpio_irq_trigger_config(PA, pin_7, both_edges_trigger);  // Configure interrupt trigger mode
eclic_irq_enable(PA_IRQn);    // Enable interrupt

Crystal I/O Examples¶

The following code controls PA0 and PA1 of the PA group in output mode:

dpmu_osc_pad_for_gpio(ENABLE);              // PA0 and PA1 used as GPIO, must disable crystal function

// PA0 initialization
scu_set_device_gate(PA, ENABLE);             // Enable GPIOA clock
dpmu_set_io_reuse(PA0, FIRST_FUNCTION);      // Initialize as GPIO function
dpmu_set_adio_reuse(PA0, DIGITAL_MODE);      // Initialize as digital function (default is analog)
dpmu_set_io_direction(PA0, DPMU_IO_DIRECTION_OUTPUT);  // Initialize pin as output mode
gpio_set_output_mode(PA, pin_0);             // Initialize GPIOA pin_0 as output mode
gpio_set_output_high_level(PA, pin_0);       // Output high level
gpio_set_output_low_level(PA, pin_0);        // Output low level

// PA1 initialization
scu_set_device_gate(PA, ENABLE);             // Enable GPIOA clock
dpmu_set_io_reuse(PA1, FIRST_FUNCTION);      // Initialize as GPIO function
dpmu_set_adio_reuse(PA1, DIGITAL_MODE);      // Initialize as digital function (default is analog)
dpmu_set_io_direction(PA1, DPMU_IO_DIRECTION_OUTPUT);  // Initialize pin as output mode
gpio_set_output_mode(PA, pin_1);             // Initialize GPIOA pin_1 as output mode
gpio_set_output_high_level(PA, pin_1);       // Output high level
gpio_set_output_low_level(PA, pin_1);        // Output low level

The following code controls PA0 and PA1 of the PA group in input mode:

dpmu_osc_pad_for_gpio(ENABLE);              // PA0 and PA1 used as GPIO, must disable crystal function

// PA0 initialization
scu_set_device_gate(PA, ENABLE);             // Enable GPIOA clock
dpmu_set_io_reuse(PA0, FIRST_FUNCTION);      // Initialize as GPIO function
dpmu_set_adio_reuse(PA0, DIGITAL_MODE);      // Initialize as digital function (default is analog)
dpmu_set_io_direction(PA0, DPMU_IO_DIRECTION_INPUT);  // Initialize pin as input mode
gpio_set_input_mode(PA, pin_0);              // Initialize GPIOA pin_0 as input mode
if (0 == gpio_get_input_level_single(PA, pin_0)) {   // Get I/O level
    // INFO: Input is low level
} else {
    // INFO: Input is high level
}

// PA1 initialization
scu_set_device_gate(PA, ENABLE);             // Enable GPIOA clock
dpmu_set_io_reuse(PA1, FIRST_FUNCTION);      // Initialize as GPIO function
dpmu_set_adio_reuse(PA1, DIGITAL_MODE);      // Initialize as digital function (default is analog)
dpmu_set_io_direction(PA1, DPMU_IO_DIRECTION_INPUT);  // Initialize pin as input mode
gpio_set_input_mode(PA, pin_1);              // Initialize GPIOA pin_1 as input mode
if (0 == gpio_get_input_level_single(PA, pin_1)) {   // Get I/O level
    // INFO: Input is low level
} else {
    // INFO: Input is high level
}

The following code configures PA0 and PA1 of the PA group for both-edge triggered interrupt:

dpmu_osc_pad_for_gpio(ENABLE);              // PA0 and PA1 used as GPIO, must disable crystal function

// PA0 initialization
scu_set_device_gate(PA, ENABLE);             // Enable GPIOA clock
dpmu_set_io_reuse(PA0, FIRST_FUNCTION);      // Initialize as GPIO function
dpmu_set_adio_reuse(PA0, DIGITAL_MODE);      // Initialize as digital function (default is analog)
dpmu_set_io_direction(PA0, DPMU_IO_DIRECTION_INPUT);  // Initialize pin as input mode
gpio_set_input_mode(PA, pin_0);              // Initialize GPIOA pin_0 as input mode
gpio_irq_trigger_config(PA, pin_0, both_edges_trigger);  // Configure interrupt trigger mode
eclic_irq_enable(PA_IRQn);                  // Enable interrupt

// PA1 initialization
scu_set_device_gate(PA, ENABLE);             // Enable GPIOA clock
dpmu_set_io_reuse(PA1, FIRST_FUNCTION);      // Initialize as GPIO function
dpmu_set_adio_reuse(PA1, DIGITAL_MODE);      // Initialize as digital function (default is analog)
dpmu_set_io_direction(PA1, DPMU_IO_DIRECTION_INPUT);  // Initialize pin as input mode
gpio_set_input_mode(PA, pin_1);              // Initialize GPIOA pin_1 as input mode
gpio_irq_trigger_config(PA, pin_1, both_edges_trigger);// Configure interrupt trigger mode
eclic_irq_enable(PA_IRQn);                  // Enable interrupt